XA3S1500-4FGG456I Datasheet, PDF (6/8 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

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Introduction and Ordering Information
Table 5: Quiescent Supply Current Characteristics
Symbol
Description
Device
I-Grade
Maximum
Q-Grade
Maximum
Units
I_CCINTQ
Quiescent V_CCINT supply current
XA3S50
50
100
mA
XA3S200
125
200
mA
XA3S400
180
250
mA
XA3S1000
315
400
mA
XA3S1500
410
-
mA
I_CCOQ
Quiescent V_CCO supply current
XA3S50
12
12
mA
XA3S200
12
12
mA
XA3S400
14
14
mA
XA3S1000
14
14
mA
XA3S1500
16
-
mA
I_CCAUXQ
Quiescent V_CCAUX supply current
XA3S50
22
25
mA
XA3S200
33
35
mA
XA3S400
44
50
mA
XA3S1000
55
60
mA
XA3S1500
85
-
mA
Notes:
1. The numbers in this table are based on the conditions set forth in Table 31 of DS099. Quiescent supply current is measured with all
I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are
characterized using devices with typical processing at ambient room temperature (T_A of 25°C at V_CCINT = 1.2V, V_CCO = 3.3V, and
V_CCAUX = 2.5V). Maximum values are the production test limits measured for each device at the maximum specified junction
temperature and at maximum voltage limits with V_CCINT = 1.26V, V_CCO = 3.45V, and V_CCAUX = 2.625V. The FPGA is programmed
with a “blank” configuration data file (i.e., a design with no functional elements instantiated). For conditions other than those
described above, (e.g., a design including functional elements, the use of DCI standards, etc.), measured quiescent current levels
may be different than the values in the table. Use the XPower Power Estimator for more accurate estimates. See Note 2.
2. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The
XPower Power Estimator at http://www.xilinx.com/ise/power_tools provides quick, approximate, typical estimates, and does not
require a netlist of the design. b) XPower, part of the Xilinx ISE development software, uses the FPGA netlist as input to provide more
accurate maximum and typical estimates.
3. The maximum numbers in this table also indicate the minimum current each power rail requires in order for the FPGA to power-on
successfully, once all three rails are supplied. If V_CCINT is applied before V_CCAUX, there may be temporary additional I_CCINT current
until V_CCAUX is applied. See Surplus ICCINT if VCCINT Applied before VCCAUX, page 51 of DS099.
Ordering Information
BGA Ball A1
Device Type
Package
Speed Grade
Temperature Range
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SPARTAN ^R
XA3S1000^TM
FTG256EGQ0525
D1234567A
4Q
Mask Revision Code
Fabrication Code
Process Code
Date Code
Lot Code
DS314-1_02_100808
Figure 2: Spartan-3 BGA Package Marking Example for Part Number XA3S1000-4 FTG256Q
Spartan-3 FPGAs are available in Pb-free packaging options for all device/package combinations. The Pb-free packages
include a special “G” character in the ordering code.
DS314 (v1.3) June 18, 2009
www.xilinx.com
Product Specification
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