DS805 Datasheet, PDF (7/7 Pages) Xilinx, Inc – The external master interface ports directly connect

LogiCORE™ IP AXI External Slave Connector (v1.00.a)
Table 4: Parameters (Cont’d)
Parameter Name
Default Value
Allowable
Values
Description
C_S_AXI_NUM_MEM_ADDR_RANGES
0
0-4
Number of memory-type address ranges (allows
caching).
1. The user must set the values of at least C_S_AXI_RNG0_BASEADDR and C_S_AXI_RNG0_HIGHADDR. When used, each
C_S_AXI_RNGn_BASEADDR must be a multiple of the range size (aligned), where the range size is C_S_AXI_RNGn_HIGHADDR -
C_S_AXI_RNGn_BASEADDR + 1. Each range size must be a power of 2 and at least 4K.
2. Default values indicate unused address ranges.
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Revision History
The following table shows the revision history for this document:
Date
09/21/2010
01/18/2012
Version
1.00
1.1
Description of Revisions
Initial Xilinx release.
Added the following parameters:
• C_S_AXI_MEM_RNG0-3_BASEADDR
• C_S_AXI_MEM_RNG0-3_HIGHADDR
• C_S_AXI_NUM_ADDR_RANGES
• C_S_AXI_NUM_MEM_ADDR_RANGES
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DS805 January 18, 2012
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Product Specification