DS805 Datasheet, PDF (5/7 Pages) Xilinx, Inc – The external master interface ports directly connect

LogiCORE™ IP AXI External Slave Connector (v1.00.a)
Table 2: External AXI Master I/O Signals (Cont’d)
Signal Name
Signal
Init
Type Status
Description
M_AXI_BUSER
[C_S_AXI_BUSER_WIDTH-1:0]
B
I
User-defined B Channel signals.
M_AXI_BVALID
B
I
AXI write response valid.
M_AXI_BREADY
B
O
Write response ready.
AXI Read Address Channel Signals (AR)
M_AXI_ARID [C_S_AXI_ID_WIDTH-1:0]
AR
O
AXI address read ID.
M_AXI_ARADDR
[C_S_AXI_ADDR_WIDTH-1:0]
AR
O
AXI read address.
M_AXI_ARLEN [7:0]
AR
O
AXI address read burst length.
M_AXI_ARSIZE [2:0]
AR
O
AXI address read burst size.
M_AXI_ARBURST [1:0]
M_AXI_ARLOCK
M_AXI_ARCACHE [3:0]
AR
O
AXI address read burst type.
AR
O
AXI read address lock signal. ⁽¹⁾
AR
O
AXI read address cache control signal. ⁽¹⁾
M_AXI_ARPROT [2:0]
M_AXI_ARREGION [3:0]
M_AXI_ARQOS [3:0]
AR
O
AXI read address protection signal. ⁽¹⁾
AR
O
Channel address region index. ⁽¹⁾
AR
O
AR Channel Quality of Service (QoS). ⁽¹⁾
M_AXI_ARUSER
[C_S_AXI_ARUSER_WIDTH-1:0]
AR
O
User-defined AR Channel signals.
M_AXI_ARVALID
AR
O
AXI read address valid.
M_AXI_ARREADY
AR
I
AXI read address ready. I
AXI Read Data Channel Signals (R)
M_AXI_RID [C_S_AXI_ID_WIDTH-1:0]
R
I
AXI read data response ID.
M_AXI_RDATA
[C_S_AXI_DATA_WIDTH-1:0]
R
I
AXI Read data.
M_AXI_RRESP [1:0]
R
I
AXI Read response code.
M_AXI_RLAST
R
I
AXI read data last signal.
M_AXI_RUSER
[C_S_AXI_RUSER_WIDTH-1:0]
R
I
User-defined Channel Signals.
M_AXI_RVALID
R
I
AXI read valid.
M_AXI_RREADY
R
O
Read ready.
1. Advanced signal available for connection only when C_USE_ADVANCED_PORTS=1.
Global I/O Signals
Table 3 lists global signals of the IP.
.
Table 3: Global I/O Signals
Signal Name
Global Signals
ACLK
ARESETN
Interface
Signal
Type
Global
I
Global
I
Init
Status
Description
AXI Bus Clock.
AXI active-Low reset.
DS805 January 18, 2012
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Product Specification