DS805 Datasheet, PDF (4/7 Pages) Xilinx, Inc – The external master interface ports directly connect

LogiCORE™ IP AXI External Slave Connector (v1.00.a)
Table 1: AXI Slave Interface Signals (Cont’d)
Signal Name
Interface
S_AXI_RUSER [C_S_AXI_RUSER_WIDTH-1:0]
R
S_AXI_RVALID
R
S_AXI_RREADY
R
Signal
Type
O
O
I
Description
User-defined R Channel signals.
AXI read valid.
Read ready.
External AXI Master I/O Signals
Table 2 lists the AXI Master interface signals that can connect to embedded system ports.
.
Table 2: External AXI Master I/O Signals
Signal Name
Signal
Init
Type Status
Description
AXI Write Address Channel Signals (AW)
M_AXI_AWID [C_S_AXI_ID_WIDTH-1:0]
AW
O
AXI address write ID.
M_AXI_AWADDR
[C_S_AXI_ADDR_WIDTH-1:0]
AW
O
AXI Write address.
M_AXI_AWLEN [7:0]
AW
O
AXI address write burst length.
M_AXI_AWSIZE [2:0]
AW
O
AXI address write burst size.
M_AXI_AWBURST [1:0]
AW
O
AXI address write burst type.
M_AXI_AWLOCK
AW
O
AXI write address lock signal.
M_AXI_AWCACHE [3:0]
AW
O
AXI write address cache control signal. ⁽¹⁾
M_AXI_AWPROT [2:0]
AW
O
AXI write address protection signal. ⁽¹⁾
M_AXI_AWREGION [3:0]
AW
O
Write Address Channel address region index. ⁽¹⁾
M_AXI_AWQOS [3:0]
AW
O
Write Address Channel Quality of Service (QoS). ⁽¹⁾
M_AXI_AWUSER
[C_S_AXI_AWUSER_WIDTH-1:0]
AW
O
User-defined AW Channel signals.
M_AXI_AWVALID
AW
O
AXI write address valid.
M_AXI_AWREADY
AW
I
AXI write address ready.
AXI Write Data Channel Signals (W)
M_AXI_WID [C_S_AXI_ID_WIDTH-1:0]
W
O
AXI3 write ID.
M_AXI_WUSER
[C_S_AXI_WUSER_WIDTH-1:0]
W
O
User-defined W Channel signals.
M_AXI_WDATA
C_S_AXI_DATA_WIDTH-1:0]
W
O
AXI write data.
M_AXI_WSTRB [C_S_AXI_DATA_
WIDTH/8-1:0]
W
O
AXI write data strobes.
M_AXI_WLAST
W
O
AXI write data last signal.
M_AXI_WVALID
W
O
AXI write data valid.
M_AXI_WREADY
W
I
AXI write data ready.
AXI Write Response Channel Signals (B)
M_AXI_BID [C_S_AXI_ID_WIDTH-1:0]
B
I
AXI write data response ID.
M_AXI_BRESP [1:0]
B
I
AXI write response code.
1. Advanced signal available for connection only when C_USE_ADVANCED_PORTS=1.
DS805 January 18, 2012
www.xilinx.com
4
Product Specification