DS805 Datasheet, PDF (2/7 Pages) Xilinx, Inc – The external master interface ports directly connect

LogiCORE™ IP AXI External Slave Connector (v1.00.a)
Functional Description
Figure 1 illustrates the AXI external slave connection to an AXI Interconnect.
X-Ref Target - Figure 1
%$+SUB SYSTEM
-ICROBLAZE
)#!8)
3?!8)
-EMORYCONTROLLER
$#!8)
!XI?INTERCONNECT 3?!8)
!XI?GPIO
)NDIVIDUAL!8)0ORTSMADE
EXTERNALTOSUB SYSTEM
INTERFACE
3?!8)
!XI?EXT?SLAVE?CONN
8
Figure 1: System Using AXI External Slave Connector
I/O Signals
AXI Slave Interface Signals
Table 1 lists the slave interface signals that can connect to an axi_interconnect IP in the embedded system.
Table 1: AXI Slave Interface Signals
Signal Name
Interface
AXI Write Address Channel Signals (AW)
S_AXI_AWID [C_S_AXI_ID_WIDTH-1:0]
AW
S_AXI_AWADDR
[C_S_AXI_ADDR_WIDTH-1:0]
AW
S_AXI_AWLEN [7:0]
AW
S_AXI_AWSIZE [2:0]
AW
S_AXI_AWBURST [1:0]
AW
S_AXI_AWLOCK
AW
S_AXI_AWCACHE [3:0]
AW
S_AXI_AWPROT [2:0]
AW
S_AXI_AWREGION [3:0]
AW
S_AXI_AWQOS [3:0]
AW
S_AXI_AWUSER
[C_S_AXI_AWUSER_WIDTH-1:0]
AW
Signal
Type
I
I
I
I
I
I
I
I
I
I
I
Description
AXI address Write ID.
AXI Write address.
AXI address write burst length.
AXI address write burst size.
AXI address write burst type.
AXI write address lock signal.
AXI write address cache control signal.
AXI write address protection signal.
Channel address region index
Channel Quality of Service (QoS).
User-defined AW Channel signals.
DS805 January 18, 2012
www.xilinx.com
2
Product Specification