DS804 Datasheet, PDF (7/7 Pages) Xilinx, Inc – The following tables list the external slave signals and master

LogiCORE™ IP AXI External Master Connector (v1.00.a)
Table 4: External Master Parameters (Cont’d)
Parameter Name
Default Value
C_M_AXI_ARUSER_WIDTH
1
C_M_AXI_WUSER_WIDTH
1
C_M_AXI_RUSER_WIDTH
1
Allowable
Values
Integer
(1-2147483647
Integer
(1-2147483647
Integer
(1-2147483647
Description
Specifies the number of ARUSER bits on the
connected external master device.
Specifies the number of WUSER bits on the
connected external master device.
Specifies the number of RUSER bits on the
connected external master device.
Support
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changes are made to any section of the design labeled DO NOT MODIFY.
Revision History
The following table shows the revision history for this document:
Date
09/21/2010
Version
1.00
Initial Xilinx release.
Description of Revisions
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DS804 September 21, 2010
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Product Specification