DS804 Datasheet, PDF (4/7 Pages) Xilinx, Inc – The following tables list the external slave signals and master

LogiCORE™ IP AXI External Master Connector (v1.00.a)
Table 1: I/O Slave Signals (Cont’d)
Signal Name
Interface
Signal
Type
Description
S_AXI_RLAST
R
O
AXI Read data last signal.
S_AXI_RUSER [C_S_AXI_RUSER_WIDTH-1:0]
R
O
User-defined R Channel signals.
S_AXI_RVALID
R
O
AXI Read valid.
S_AXI_RREADY
R
I
Read ready.
1. Advanced signal available for connection only when C_USE_ADVANCED_PORTS=1.
AXI Master Interface Signals
Table 2 lists the master interface signals that can connect to an AXI Interconnect IP in an embedded system.
Table 2: AXI Master Interface Signals
Signal Name
Interface
AXI Write Address Channel Signals (AW)
M_AXI_AWID
[C_M_AXI_THREAD_ID_WIDTH-1:0]
AW
M_AXI_AWADDR
[C_M_AXI_ADDR_WIDTH-1:0]
AW
M_AXI_AWLEN [7:0]
AW
M_AXI_AWSIZE [2:0]
AW
M_AXI_AWBURST [1:0]
AW
M_AXI_AWLOCK
AW
M_AXI_AWCACHE [3:0]
AW
M_AXI_AWPROT [2:0]
AW
M_AXI_AWQOS [3:0]
AW
M_AXI_AWUSER
[C_M_AXI_AWUSER_WIDTH-1:0]
AW
M_AXI_AWVALID
AW
M_AXI_AWREADY
AW
AXI Write Data Channel Signals (W)
M_AXI_WDATA
W
[C_M_AXI_DATA_WIDTH-1:0]
M_AXI_WSTRB
[C_M_AXI_DATA_WIDTH/8-1:0]
W
M_AXI_WLAST
W
M_AXI_WUSER
[C_M_AXI_WUSER_WIDTH-1:0]
W
M_AXI_WVALID
W
Signal
Type
O
O
O
O
O
O
O
O
O
O
O
I
O
O
O
O
O
Description
AXI address Write ID.
AXI Write address.
AXI address Write burst length.
AXI address Write burst size.
AXI address Write burst type.
AXI Write address lock signal.
AXI Write address cache control signal.
AXI Write address protection signal.
Channel Quality of Service (QoS).
User-defined AW Channel signals.
AXI Write address valid.
AXI Write address ready.
AXI Write data.
AXI Write data strobes.
AXI Write data last signal. Indicates the last transfer in a Write
burst.
User-defined W Channel signals.
AXI Write data valid.
AXI Write data ready.
M_AXI_WREADY
W
I
DS804 September 21, 2010
www.xilinx.com
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Product Specification