DS804 Datasheet, PDF (2/7 Pages) Xilinx, Inc – The following tables list the external slave signals and master

LogiCORE™ IP AXI External Master Connector (v1.00.a)
Feature Description
The following figure illustrates the AXI external master connection to an AXI Interconnect.
X-Ref Target - Figure 1
EDK sub-system
Microblaze
ICAXI
DCAXI
Axi_interconnect S_AXI
Individual AXI Ports made
external to sub-system
interface
Axi_ext_master_conn
M_AXI
Memory controller
Figure 1: System Using AXI External Master Connector
I/O Signals
The following tables list the external slave signals and master I/O signals.
External Slave Signals
Table 1 lists the external AXI slave interface signals that can connect to embedded system ports.
Table 1: I/O Slave Signals
Signal Name
Interface
Signal
Type
Description
AXI Write Address Channel Signals (AW)
S_AXI_AWLEN [7:0]
AW
I
AXI address Write burst length.
S_AXI_AWSIZE [2:0]
AW
I
AXI address Write burst size.
S_AXI_AWBURST [1:0]
AW
I
AXI address Write burst type.
S_AXI_AWLOCK
AW
I
AXI Write address lock signal. ⁽¹⁾
S_AXI_AWCACHE [3:0]
AW
I
AXI Write address cache control signal.
S_AXI_AWPROT [2:0]
AW
I
AXI Write address protection signal.
S_AXI_AWQOS [3:0]
AW
I
Channel Quality of Service (QoS). ⁽¹⁾
S_AXI_AWUSER
[C_M_AXI_AWUSER_WIDTH-1:0]
AW
I
User-defined AW Channel signals.
S_AXI_AWVALID
AW
I
AXI Write address valid.
1. Advanced signal available for connection only when C_USE_ADVANCED_PORTS=1.
X12040
DS804 September 21, 2010
www.xilinx.com
2
Product Specification