DS804 Datasheet, PDF (6/7 Pages) Xilinx, Inc – The following tables list the external slave signals and master

LogiCORE™ IP AXI External Master Connector (v1.00.a)
Global I/O Signals
Table 3 lists global signals of the IP.
Table 3: Global I/O Signals
Signal Name
Global Signals
ACLK
ARESETN
Interface
Signal
Type
Global
I
Global
I
Init
Status
Description
AXI Bus Clock.
AXI active-Low reset.
Parameters
Table 4 lists the user-visible parameters. In addition to the parameters listed in this table, there are also inferred
parameters for the M_AXI interface in the EDK tools. Through the design, these inferred parameters control the
behavior of the AXI Interconnect. For a complete list of the interconnect settings related to the AXI interface, see the
AXI Interconnect IP Data Sheet (DS768).
Table 4: External Master Parameters
Parameter Name
Default Value
C_USE_ADVANCED_PORTS
0
C_M_AXI_PROTOCOL
C_M_AXI_ADDR_WIDTH
C_M_AXI_DATA_WIDTH
C_M_AXI_SUPPORTS_READ
C_M_AXI_SUPPORTS_WRITE
C_M_AXI_SUPPORTS_THREADS
C_M_AXI_THREAD_ID_WIDTH
C_M_AXI_SUPPORTS_NARROW_BURST
AXI4
32
32
1
1
0
1
1
C_M_AXI_SUPPORTS_USER_SIGNALS
0
C_M_AXI_AWUSER_WIDTH
1
C_M_AXI_BUSER_WIDTH
1
Allowable
Values
Description
Controls whether the less-common (advanced)
0, 1
AXI signals are included in the external slave
interface.
String
(AXI3, AXI4,
AXI4LITE
AXI protocol used by the connected external
master device.
constant
(32)
Width of ADDR signals (both S and M
interfaces).
Integer
Specifies the width of the WDATA and RDATA
signals used by the connected external master
(32, 64, 128, 256) _{device (applies to both S and M interfaces).}
0,1
Specifies whether the connected external master
device performs reads.
0,1
Specifies whether the connected external master
device performs Writes.
Specifies whether the connected external master
0,1
device produces any ID signals (has reordering
depth > 1).
1-16
Specifies the number of ID bits produced by the
connected external master device.
Specifies whether the connected external master
0,1
device produces “narrow bursts” (transfer SIZE
less than data width for any multi-beat bursts).
Specifies whether the connected external master
0,1
device has any USER signals on any AXI
channels.
Integer
Specifies the number of AWUSER bits on the
(1-2147483647 connected external master device.
Integer
Specifies the number of BUSER bits on the
(1-2147483647 connected external master device.
DS804 September 21, 2010
www.xilinx.com
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Product Specification