DS804 Datasheet, PDF (5/7 Pages) Xilinx, Inc – The following tables list the external slave signals and master

LogiCORE™ IP AXI External Master Connector (v1.00.a)
Table 2: AXI Master Interface Signals (Cont’d)
Signal Name
Interface
AXI Write Response Channel Signals (B)
M_AXI_BID
[C_M_AXI_THREAD_ID_WIDTH-1:0]
B
M_AXI_BRESP [1:0]
B
M_AXI_BUSER
B
M_AXI_BVALID
B
M_AXI_BREADY
B
AXI Read Address Channel Signals (AR)
M_AXI_ARID [C_S_AXI_ID_WIDTH-1:0]
AR
M_AXI_ARADDR
[C_S_AXI_ADDR_WIDTH-1:0]
AR
M_AXI_ARLEN [7:0]
AR
M_AXI_ARSIZE [2:0]
AR
M_AXI_ARBURST [1:0]
AR
M_AXI_ARLOCK
AR
M_AXI_ARCACHE [3:0]
AR
M_AXI_ARPROT [2:0]
AR
M_AXI_ARQOS [3:0]
AR
M_AXI_ARUSER
[C_S_AXI_ARUSER_WIDTH-1:0]
AR
M_AXI_ARVALID
AR
M_AXI_ARREADY
AR
AXI Read Data Channel Signals (R)
M_AXI_RID [C_S_AXI_ID_WIDTH-1:0]
R
M_AXI_RDATA [C_S_AXI_DATA_WIDTH-1:0]
R
M_AXI_RRESP [1:0]
R
M_AXI_RLAST
R
M_AXI_RUSER
[C_S_AXI_RUSER_WIDTH-1:0]
R
M_AXI_RVALID
R
M_AXI_RREADY
R
Signal
Type
I
I
I
O
I
O
O
O
O
O
O
O
O
O
I
O
I
I
I
I
I
I
I
O
Description
AXI Write response ID.
AXI Write response code.
User-defined B Channel signals.
AXI Write response valid.
Write response ready.
AXI address read ID.
AXI read address.
AXI address read burst length.
AXI address read burst size.
AXI address read burst type.
AXI read address lock signal.
AXI read address cache control signal.
AXI read address protection signal.
AR Channel Quality of Service (QoS).
User-defined AR Channel signals.
AXI read address valid.
AXI read address ready.
AXI read data response ID.
AXI Read data.
AXI Read response code.
AXI read data last signal.
User-defined R Channel signals.
AXI read valid.
Read ready.
DS804 September 21, 2010
www.xilinx.com
5
Product Specification