DS480 Datasheet, PDF (6/6 Pages) Xilinx, Inc – Single master - no bus arbitration logic

Data Side OCM Bus v1.0
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Reference Documents
1. UG018 PowerPC 405 Processor Block Reference Guide
2. DS447 Data Side OCM BRAM Interface Controller Data Sheet
Revision History
Date
6/16/04
8/17/04
9/22/04
8/2/05
1/23/07
4/24/09
Version
1.0
1.1
1.2
1.3
1.4
1.5
Revision
Initial Xilinx release
Updated for EDK 6.3. Updated trademarks and supported device family listing.
Updated to new data sheet template
Updated to new DS template.
Fixed RdDBus mux error for 5 slave case.
Replaced references to supported device families and tool name(s) with hyperlink
to PDF file.
Notice of Disclaimer
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with no warranty of any kind, express or implied. Xilinx makes no representation that the Information,
or any particular implementation thereof, is free from any claims of infringement. You are responsible
for obtaining any rights you may require for any implementation based on the Information. All
specifications are subject to change without notice. XILINX EXPRESSLY DISCLAIMS ANY
WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE INFORMATION OR
ANY IMPLEMENTATION BASED THEREON, INCLUDING BUT NOT LIMITED TO ANY
WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS
OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
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any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,
without the prior written consent of Xilinx.
6
www.xilinx.com
DS480 April 24, 2009
Product Specification