DS480 Datasheet, PDF (3/6 Pages) Xilinx, Inc – Single master - no bus arbitration logic

Data Side OCM Bus v1.0
Table 1: Data Side OCM Bus I/O (Contd)
Signal
I/O
Connect
s to
Description
S_BRAMDSOCMRDDBUS I
slaves
This signal connects directly to the output
BRAMDSOCMRDDBUS.
DSOCMRDADDRVALID
Virtex-4 only. Single cycle read request indicating that
O
slave address is valid. Used with variable latency (non-BRAM)
slaves
DSOCMWRADDRVALID
Virtex-4 only. Single cycle write request indicating that
O
slave address and write data are valid. Used with variable latency
(non-BRAM) slaves
DSOCMRWCOMPLETE
Virtex-4 only. Acknowledge that access has been completed
O ppc405 by variable latency (non-BRAM) slave. Read data should be
valid
BRAMDSOCMRDDBUS
O ppc405 Read access read-data
DSARCVALUE
O
ppc405
DSOCM power-on16MB address window offset. The value
of this signal is set by the parameter C_DSARCVALUE.
DSCNTLVALUE
O
ppc405
DSOCM power-on configuration. The value of this signal is
set by the parameter C_DSCNTLVALUE.
DSOCMBRAMEN
O
slave Memory enable signal for BRAM
DSOCMBRAMWRDBUS
O
slave Write access write-data
DSOCMBRAMBYTEWRITE O
slave Write access byte enable
DSOCMBRAMABUS
O
slave Read/Write access address bus
DSOCMBUSY
O
slave DCR writable control signal. Reflects DSCNTL(2)
DS480 April 24, 2009
www.xilinx.com
3
Product Specification