DS480 Datasheet, PDF (2/6 Pages) Xilinx, Inc – Single master - no bus arbitration logic

Data Side OCM Bus v1.0
Functional Description
The DSOCM_V10 core shown in Figure 1 is a data-side On-Chip Memory (OCM) bus interconnect core.
The signals shown in the block diagram are listed and described in Table 1.
Figure Top x-ref 1
From system
DSOCM_Cck
SYS_Rst
To and from
PPC405 or PPC405_virtex
DSARCVALUE(0:7)
DSCNTLVALUE(0:7)
M_DSOCM*
Data Side
OCM Bus
Data Side OCM
Bus Peripherals
DSOCMWRADDRVALID
DSCOMRDADDRVALID
DSOCMBRAMBYTEWRITE(0:3)
DSOCMBRAMEN
DSOCMBRAMABUS(8:29)
DSOCMBRAMWRDBUS(0:31)
S_MBRAMDSOCMDRBUS(0:31)
S_BRAMDSOCMRDDBUS(0:31)
S_DSOCMRWCOMPLETE
S_DSOCMRWCOMPLETE
S_DSOCMSLAVESELECT
DSOCMBUSY
DS480_01_031309
Figure 1: Data-side OCM Bus Block Diagram
Data Side OCM Bus I/O Signals
Table 1: Data Side OCM Bus I/O
Signal
I/O
Connect
s to
Description
DSOCM_Clk
I
SYS_Rst
I
DSOCM_RST
O
M_DSOCMBRAMABUS
I
M_DSOCMBRAMEN
I
M_DSOCMRDADDRVALID I
M_DSOCMWRADDRVALID I
M_DSOCMBRAMWRDBUS I
M_DSOCMBRAMBYTE
WRITE
I
M_DSOCMBUSY
I
S_DSOCMSLAVESELECT I
S_DSOCMRWCOMPLETE I
system
system
slaves
ppc405
ppc405
ppc405
ppc405
ppc405
Unused
Drives the output DSOCM_RST
Reset signal for DSOCM slave peripherals
Drives the output DSOCMBRAMABUS
Drives the output DSOCMBRAMEN
Drives the output DSOCMRDADDRVALID
Drives the output DSOCMWRADDRVALID
Drives the output DSOCMBRAMWRDBUS.
ppc405 Drives the output DSOCMBRAMBYTEWRITE.
ppc405
slaves
slaves
Drives the output DSOCMBUSY.
Acknowledge signal from addressed slave. Controls read
data multiplexing in multi-slave system.
Virtex^®-4 only. Drives the output DSOCMRWCOMPLETE
2
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DS480 April 24, 2009
Product Specification