DS480 Datasheet, PDF (5/6 Pages) Xilinx, Inc – Single master - no bus arbitration logic

Data Side OCM Bus v1.0
Multi-Slave Configuration
This version of the bus can handle multiple slaves. Slave address ranges must be non-overlapping and
each slave core is responsible for its own address range check. All readable slaves must follow one of
two methods for returning data:
1. Provide an acknowledge signal (S_DSOCMSLAVESELECT) which they raise when addressed.
When not addressed this signal must be held Low. The slave read-data is ignored when the
acknowledge is Low. The DSOCM bus use the acknowledge signal as a valid signal to multiplex
read-data.
1. Always provide a High acknowledge signal, but drive all 0’s (zeros) on read-data when not
addressed.
Data Side OCM Bus Register Descriptions
There are no registers in this core.
Data Side OCM Bus Interrupt Descriptions
There are no interrupts associated with this core.
Design Implementation
Design Tools
The Data Side OCM Bus design is handwritten.
Xilinx XST is the synthesis tool used for synthesizing the Data Side OCM Bus.
Target Technology
The target technology is an FPGA listed in EDK Supported Device Families.
Device Utilization and Performance Benchmarks
Table 4: Data Side OCM Bus Resource Utilization
Parameters
C_NUM_SLAVES = 1
C_NUM_SLAVES = 2
C_NUM_SLAVES = 3
C_NUM_SLAVES = 4
Flip-Flops
0
0
0
0
Resources
4-input LUTs
0
32
64
96
There are no performance benchmarks available.
Specification Exceptions
Not applicable.
DS480 April 24, 2009
www.xilinx.com
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Product Specification