DS480 Datasheet, PDF (1/6 Pages) Xilinx, Inc – Single master - no bus arbitration logic

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Data Side OCM Bus v1.0
DS480 April 24, 2009
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Product Specification
Introduction
The DSOCM_V10 core is a data-side On-Chip Memory
(OCM) bus interconnect core. The core connects the
PowerPC^® 405 processor data-side OCM interface to
OCM peripherals, such as the data-side OCM BRAM
controller (DSBRAM IF CNTRL). For information
about the PowerPC 405 processor OCM controller
interface, see the PowerPC 405 Processor Block Reference
Guide.
Features
• Single master - no bus arbitration logic
• Configurable multiple slave capability - contains
read-data multiplexing when used with 2 or more
slaves
LogiCore Facts
Core Specifics
Supported Device
Family
See EDK Supported Device
Families.
Version of Core
dsocm_v10
v2.00b
Resources Used
Min
Max
Slices
LUTs
0
N/A
0
64 ¹
FFs
0
0
Block RAMs
0
0
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation Template
N/A
Reference Designs
N/A
Design Tool Requirements
Xilinx Implementation
Tools
Verification
Simulation
See Tools for requirements.
Synthesis
Support
Provided by Xilinx, Inc.
1. Example for 3 slaves. Size increases with number of slaves
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DS480 April 24, 2009
www.xilinx.com
1
Product Specification