DS849 Datasheet, PDF (5/10 Pages) Xilinx, Inc – LogiCORE IP Spartan-6 FPGA Triple-Rate SDI v1.0

LogiCORE IP Spartan-6 FPGA Triple-Rate SDI v1.0
Table 2: Supported Video Formats (Cont’d)
Interface
Video Standard Sampling Structure / Bit Depth
Frame/Field Rate (Hz)
Dual Link
HD-SDI
SMPTE 372
SMPTE 274
4:2:2 Y'C_B'C_R' 10-bit
4:4:4 or 4:4:4:4 Y'C_B'C_R' or RGB 10-bit
1080p: 50, 59.94, 60
1080p: 23.98, 24, 25, 29.97, 30
1080i: 50, 59.94, 60
1080PsF: 23.98, 24, 25, 29.97, 30
4:4:4 Y'C_B'C_R' or RGB 12-bit
1080p: 23.98, 24, 25, 29.97, 30
1080i: 50, 59.94, 60
1080PsF: 23.98, 24, 25, 29.97, 30
4:2:2 Y'C_B'C_R' 12-bit
1080p: 23.98, 24, 25, 29.97, 30
1080i: 50, 59.94, 60
1080PsF: 23.98, 24, 25, 29.97, 30
SMPTE 428-9 4:4:4 X'Y'Z' 12-bit
2048 X 1080p: 24
SMPTE 428-19 4:4:4 X'Y'Z' 12-bit
1080p: 25, 30
1080PsF: 25, 30
SMPTE 2048-2
4:2:2 Y'C_B'C_R' 10-bit
4:4:4 Y'C_B'C_R' or RGB 10-bit
4:4:4:4 Y'C_B'C_R'A or RGBA 10-bit
4:4:4 Y'C_B'C_R' or RGB 12-bit
1080p: 47.95, 48, 50, 59.94, 60
1080p: 23.98, 24, 25, 29.97, 30
1080PsF: 23.98, 24, 25, 29.97, 30
1080p: 23.98, 24, 25, 29.97, 30
1080PsF: 23.98, 24, 25, 29.97, 30
4:2:2 Y'C_B'C_R' 12-bit
4:2:2 Y'C_B'C_R'A 12-bit
1080p: 23.98, 24, 25, 29.97, 30
1080PsF: 23.98, 24, 25, 29.97, 30
Functional Overview
The LogiCORE IP Spartan-6 FPGA Triple-Rate SDI solution provides a combined SDI receiver and transmitter core.
The SDI receiver and transmitter share a reference clock, but can run at different bit rates and different SDI modes.
For example, the receiver can receive a 270 Mb/s SD-SDI signal while the transmitter sends a 2.97/1.001 Gb/s
3G-SDI signal. When both the RX and TX are used, the reference clock frequency is determined by the TX
requirements.
The Spartan-6 FPGA Triple-Rate SDI core must be connected to a high-speed transceiver for serialization and
deserialization of the SDI bitstream. The core is compatible with the Spartan-6 FPGA GTP transceiver. Figure 1
shows the combined receive/transmit configuration.
DS849 June 22, 2011
www.xilinx.com
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Product Specification