DS849 Datasheet, PDF (10/10 Pages) Xilinx, Inc – LogiCORE IP Spartan-6 FPGA Triple-Rate SDI v1.0

LogiCORE IP Spartan-6 FPGA Triple-Rate SDI v1.0
For level B, four input data streams are accepted at a nominal rate of 74.25 MHz or 74.25/1.001 MHz. For level B-DL,
these four data streams must conform to the SMPTE 372 standard. For level B-DS, these four data streams are two
luma and chroma data stream pairs, one pair for each of two separate HD-SDI signals to be aggregated and
transported on the 3G-SDI interface.
For level B, the transmitter optionally inserts SMPTE 352 packets into the A-Y and B-Y data streams and then
outputs all four data streams for further ancillary data packet insertion. The transmitter optionally inserts line
number words and generates and inserts CRC words into all four data streams. The data streams are interleaved
and scrambled and then output to the GTP transmitter for serialization.
Support
Xilinx provides technical support for this LogiCORE IP product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
This Xilinx® LogiCORE IP module is provided under the terms of the Xilinx End User License Agreement. The core
is generated using the CORE Generator™ software provided with the Xilinx ISE® Design Suite.
Contact your local Xilinx sales representative for information on pricing and availability of other Xilinx LogiCORE
IP modules. Information about additional modules can be found at the Xilinx IP Center.
Revision History
The following table shows the revision history for this document:
Date
06/22/11
Version
1.0
Initial Xilinx release.
Description of Revisions
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DS849 June 22, 2011
www.xilinx.com
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Product Specification