DS849 Datasheet, PDF (3/10 Pages) Xilinx, Inc – LogiCORE IP Spartan-6 FPGA Triple-Rate SDI v1.0

LogiCORE IP Spartan-6 FPGA Triple-Rate SDI v1.0
Table 1: Resource Usage (Cont’d)
RX/TX without RX EDH with TX EDH
LUTs
Flip-Flops
Slices⁽¹⁾
BUFG/BUFR
PLLADV
Block RAMs
DSP48A1 Slices
Transceivers
RX/TX with RX and TX EDH
LUTs
Flip-Flops
Slices⁽¹⁾
BUFG/BUFR
PLLADV
Block RAMs
DSP48A1 Slices
Transceivers
2880
2590
1440
4⁽²⁾
2
2
2
1 GTP
3300
2960
1700
4⁽²⁾
2
2
2
1 GTP
Notes:
1. Slice counts are only estimates. The exact number of slices depends on level of resource sharing with adjacent logic.
2. Generally, two global or regional clocks are used per RX or TX interface. However, an additional global clock is
required to drive the DRPCLK. But, the DRPCLK can be any clock frequency available in the FPGA that falls within
the supported DRPCLK frequency range. Multiple SDI interfaces can share the same global DRPCLK.
Supported Video Formats
Table 2 shows the video formats that are supported by the LogiCORE IP Spartan-6 FPGA Triple-Rate SDI core.
Table 2: Supported Video Formats
Interface
Video Standard Sampling Structure / Bit Depth
SD-SDI
SMPTE 259-C
HD-SDI
SMPTE 292
PAL
NTSC
SMPTE 274
4:2:2 Y'C_B'C_R' 10-bit or 8-bit
4:2:2 Y'C_B'C_R' 10-bit or 8-bit
4:2:2 Y'C_B'C_R' 10-bit
SMPTE 296
SMPTE 260
SMPTE 2048-2
4:2:2 Y'C_B'C_R' 10-bit
4:2:2 Y'C_B'C_R' 10-bit
4:2:2 Y'C_B'C_R' 10-bit
Frame/Field Rate (Hz)
50
59.94
1080p: 23.98, 24, 25, 29.97, 30
1080i: 50, 59.94, 60
1080PsF: 23.98, 24, 25, 29.97, 30
720p: 23.98, 24, 25. 29.97, 30, 50, 59.94, 60
1035i: 59.94, 60
1080p: 23.98, 24, 25, 29.97, 30
DS849 June 22, 2011
www.xilinx.com
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Product Specification