X40620 Datasheet, PDF (9/17 Pages) Xicor Inc. – Dual Voltage CPU Supervisor with 64K Serial EEPROM

X40620
Figure 10. Acknowledge Polling
SCL
8th CLK
‘ACK’
CLK
8th
‘ACK’
CLK
CLK
SDA
‘ACK’
Start
Condition
8th Bit
ACK or
no ACK
MEMORY READ OPERATIONS
Memory read operations are initiated in the same
manner as write operations but with a different com-
mand code.
Random Read
The master issues the start condition, then a Read
instruction, then issues the word address. Once the
first byte has been read, another start can be issued
followed by a new 8-bit address. See Figure 11.
Sequential Read
The host can read sequentially within the memory
array after receiving the Read Command and an
address within the address space. The data output is
sequential, with the data from address n followed by
the data from n+1. The address counter for read oper-
ations increments all address bits, allowing the entire
memory array contents to be serially read during one
operation. At the end of the address space (address
1FFFh) the device goes into an idle state and a new
read sequence must be initiated to continue reading at
another address. Refer to Figure 12 for the address,
acknowledge and data transfer sequence. An acknowl-
edge must follow each 8-bit data transfer. After the last
bit has been read, the host sends a stop condition with
or without a preceding acknowledge.
Figure 11. Random Read
SDA S
Read
Command
S
Data 0
S
Data 0
Figure 12. Sequential Read
SDA _S
Read
Command
Data 0
S
Data X
Characteristics subject to change without notice. 9 of 17