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X40620 Datasheet, PDF (1/17 Pages) Xicor Inc. – Dual Voltage CPU Supervisor with 64K Serial EEPROM
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X40620
Dual Voltage CPU Supervisor with 64K Serial EEPROM
FEATURES
• Dual Voltage Detection and Reset Assertion
—Three standard reset threshold settings. (3.1V/
2.6V, 3.1V/1.7V, 2.9V/2.3V)
—Adjust low voltage reset threshold voltages
using special programming sequence
—RESET signal valid down to VCC=1V
• Watchdog Timer (150ms)
• Power On Reset (150ms)
• Low Power CMOS
—10µA typical standby current, watchdog on
—400µA typical standby current, watchdog off
• 64kbit 2-Wire Serial EEPROM
—1MHz serial interface speed
—64-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.5 to 3.7V Power Supply Operation
• 8-Lead TSSOP package
DESCRIPTION
The X40620 combines several functions into one
device. The first is a dual voltage monitoring, power-on
reset control, watchdog timer and 64Kbit serial
EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying voltage to VCC activates the power on reset
circuit which holds RESET active for a period of time.
This allows the power supply and system oscillator to
stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the set minimum Vtrip point. RESET is
active until VCC returns to proper operating level and
stabilizes.
A second voltage monitor circuit (V2MON) tracks the
unregulated supply to provide a power fail warning or
monitors different power supply voltage. When the
second monitored voltage drops below a preset
V2TRIP voltage. V2FAIL is active until V2 returns to
proper operating level and above the V2TRIP voltage.
Five common low voltage combinations are available,
however, Xicor’s unique circuits allows the threshold
for either voltage monitor to be reprogrammed to meet
special needs or to fine-tune the threshold for applica-
tions requiring higher precision.
BLOCK DIAGRAM
WP
Write Control
Logic
SCL
SDA
Command
Decode
and
Control
Logic
HV Generation
Timing and Control
EEPROM Array
(64Kbits)
(VCC) Control Signal
Y Decoder
Data Register
Xicor, Inc. 2000 Patents Pending
9900-3003.5 4/24/00 EP
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power on and
Low Voltage
Reset
Generation
RESET
+
-
V2TRIP
+
- VTRIP
V2FAIL
V2MON
VCC
Characteristics subject to change without notice. 1 of 17