X1288 Datasheet, PDF (8/31 Pages) Xicor Inc. – 2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM

Preliminary Information
X1288
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
t_WC
Stop
Condition
Start
Condition
Power Up Timing
Symbol
Parameter
Min.
Typ.⁽²⁾
Max.
Units
t_PUR⁽¹⁾
t_PUW⁽¹⁾
Time from Power Up to Read
Time from Power Up to Write
1
ms
5
ms
Notes: (1) Delays are measured from the time V_CC is stable until the specified operation can be initiated. These parameters are not 100%
tested. V_CC slew rate should be between 0.2mV/µsec and 50mV/µsec.
(2) Typical values are for T_A = 25°C and V_CC = 5.0V
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min.
Typ.⁽¹⁾
Max.
Units
t_WC⁽¹⁾
Write Cycle Time
5
10
ms
Note: (1) t_WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS
Watchdog/Low Voltage Reset Parameters (See Figures 3 and 4)
Symbols
V_PTRIP
t_RPD
t_PURST
Parameters
Programmed Reset Trip Voltage
X1288-4.5A
X1288
X1288-2.7A
X1288-2.7
V_CC Detect to RESET LOW
Power Up Reset Time-out Delay
Min.
4.50
4.25
2.75
2.55
100
Typ.
4.63
4.38
2.85
2.65
250
Max.
4.75
4.50
2.95
2.75
500
400
Unit
V
ns
ms
t_F
t_R
t_WDO
V_CC Fall Time
V_CC Rise Time
Watchdog Timer Period (Crystal=32.768kHz):
WD1=0, WD0=0, (default)
WD1=0, WD0=1
WD1=1, WD0=0
10
µs
10
µs
1.7
1.75
1.8
s
725
750
775
ms
225
250
275
ms
t_RST
Watchdog Reset Time-out Delay (Crystal=32.768kHz)
225
250
275
ms
t_RSP
2-Wire interface
1
µs
V_RVALID Reset Valid V_CC
1.0
V
REV 1.1.30 3/24/04
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