X1288 Datasheet, PDF (22/31 Pages) Xicor Inc. – 2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM

Preliminary Information
X1288
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 14 for the address,
acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X1288 resets itself without per-
forming the write. The contents of the array are not
affected.
Acknowledge Polling
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
X1288 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do this,
the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
X1288 is still busy with the nonvolatile write cycle then
no ACK will be returned. When the X1288 has com-
pleted the write operation, an ACK is returned and the
host can proceed with the read or write operation.
Refer to the flow chart in Figure 16.
Read Operations
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the X1288 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the sixteen bit
address is initialized to 0h. In this way, a current
address read immediately after the power on reset can
download the entire contents of memory starting at the
first location.Upon receipt of the Slave Address Byte
with the R/W bit set to one, the X1288 issues an
acknowledge, then transmits eight data bits. The mas-
ter terminates the read operation by not responding
with an acknowledge during the ninth clock and issuing
a stop condition. Refer to Figure 15 for the address,
acknowledge, and data transfer sequence.
Figure 14. Page Write Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
Slave
t
Address
Word
Address 1
Word
Address 0
1
11 10 0
A
A
C
C
K
K
1 ≤ n ≤ 128 for EEPROM array
1 ≤ n ≤ 8 for CCR
Data
(1)
S
Data
(n)
t
o
p
A
A
C
C
K
K
Figure 15. Current Address Read Sequence
S
Signals from
t
a
Slave
S
t
the Master
r Address
o
t
p
SDA Bus
1
1 1 11
Signals from
the Slave
A
C
Data
K
REV 1.1.30 3/24/04
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