X1288 Datasheet, PDF (15/31 Pages) Xicor Inc. – 2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM

Preliminary Information
X1288
Table 3. Block Protect Bits
Protected
Addresses
X1288
000
None
0 0 1 6000h – 7FFFh
010
011
4000h – 7FFFh
0000h – 7FFFh
1 0 0 0000h – 007Fh
101
110
0000h – 00FFh
0000h – 01FFh
1 1 1 0000h – 03FFh
Array Lock
None (default)
Upper 1/4
Upper 1/2
Full Array
First Page
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Table 4. Watchdog Timer Time-Out Options
WD1 WD0
0
0
0
1
1
0
1
1
Watchdog Time-Out Period
1.75 seconds
750 milliseconds
250 milliseconds
Disabled (default)
INTERRUPT CONTROL AND FREQUENCY
OUTPUT REGISTER (INT)
Interrupt Control and Status Bits (IM, AL1E, AL0E)
There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output (IRQ). The interrupts are enabled when either
AL1E and AL0E are set to ‘1’, respectively.
Two volatile bits (AL1 and AL0), associated with the two
alarms respectively, indicate if an alarm has happened.
These bits are set on an alarm condition regardless of
whether the IRQ interrupt is enabled. The AL1 and AL0
bits in the status register are reset by the falling edge of
the eighth clock of a read of the register containing the
bits.
Pulse Interrupt Mode
The pulsed interrupt mode allows for repetitive or
recurring alarm functionality. Hence an repetitive or
recurring alarm can be set for every n^th second, or n^th
minute, or n^th hour, or n^th date, or for the same day of
the week. The pulsed interrupt mode can be consid-
ered a repetitive interrupt mode, with the repetition rate
set by the time setting fo the alarm.
The Pulse Interrupt Mode is enabled when the IM bit is
set.
IM Bit
Interrupt / Alarm Frequency
0 Single Time Event Set By Alarm
1 Repetitive / Recurring Time Event Set By Alarm
The Alarm IRQ output will output a single pulse of
short duration (approximately 10-40ms) once the
alarm condition is met. If the interrupt mode bit (IM bit)
is set, then this pulse will be periodic.
Programmable Frequency Output Bits—FO1, FO0
These are two output control bits. They select one of
three divisions of the internal oscillator, that is applied
to the PHZ output pin. Table 5 shows the selection bits
for this output. When using the PHZ output function,
the Alarm IRQ output function is disabled.
Table 5. Programmable Frequency Output Bits
FO1
0
0
1
1
FO0
0
1
0
1
Output Frequency
(average of 100 samples)
Alarm IRQ output
32.768kHz
100Hz
1Hz
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) — DTR2, DTR1 and
DTR0 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
REV 1.1.30 3/24/04
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