X1288 Datasheet, PDF (24/31 Pages) Xicor Inc. – 2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM

Preliminary Information
X1288
Figure 17. Random Address Read Sequence
S
S
Signals from
the Master
t
a
Slave
r ^Address
Word
Address 1
Word
Address 0
t
a Slave
r _Address
S
t
o
t
t
p
SDA Bus
1
1 110 0
Signals from
the Slave
A
A
C
C
K
K
1
A
C
K
1 1 11
A
C
K
Data
Figure 18. Sequential Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
Slave
A
A
A
t
Address
C
C
C
o
K
K
K
p
1
A
C
Data
K
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
REV 1.1.30 3/24/04
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