X1288 Datasheet, PDF(12/31 Page) Xicor Inc. – 2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM

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X1288 Datasheet, PDF (12/31 Pages) Xicor Inc. – 2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM

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Preliminary Information

X1288

frequency. For example, a >20ppm frequency deviation

translates into an accuracy of >1 minute per month.

these parameters are available from the crystal

manufacturer. Xicorâs RTC family provides on-chip crystal

compensation networks to adjust load-capacitance to

tune oscillator frequency from +116 ppm to â37 ppm

when using a 12.5 pF load crystal. For more detail

information see the Application section.

CLOCK/CONTROL REGISTERS (CCR)

The Control/Clock Registers are located in an area

separate from the EEPROM array and are only

accessible following a slave byte of â1101111xâ and

reads or writes to addresses [0000h:003Fh]. The

clock/control memory map has memory addresses

from 0000h to 003Fh. The deï¬ned addresses are

described in the Table 1. Writing to and reading from

the undeï¬ned addresses are not recommended.

CCR Access

The contents of the CCR can be modiï¬ed by perform-

ing a byte or a page write operation directly to any

address in the CCR. Prior to writing to the CCR

(except the status register), however, the WEL and

RWEL bits must be set using a two step process (See

section âWriting to the Clock/Control Registers.â)

The CCR is divided into 5 sections. These are:

1. Alarm 0 (8 bytes; non-volatile)

2. Alarm 1 (8 bytes; non-volatile)

3. Control (4 bytes; non-volatile)

4. Real Time Clock (8 bytes; volatile)

5. Status (1 byte; volatile)

Each register is read and written through buffers. The

non-volatile portion (or the counter portion of the RTC) is

updated only if RWEL is set and only after a valid write

operation and stop bit. A sequential read or page write

operation provides access to the contents of only one

section of the CCR per operation. Access to another sec-

tion requires a new operation. Continued reads or writes,

once reaching the end of a section, will wrap around to

the start of the section. A read or write can begin at any

address in the CCR.

It is not necessary to set the RWEL bit prior to writing

the status register. Section 5 supports a single byte

read or write only. Continued reads or writes from this

section terminates the operation.

The state of the CCR can be read by performing a ran-

dom read at any address in the CCR at any time. This

returns the contents of that register location. Addi-

tional registers are read by performing a sequential

read. The read instruction latches all Clock registers

into a buffer, so an update of the clock does not

change the time being read. A sequential read of the

CCR will not result in the output of data from the mem-

ory array. At the end of a read, the master supplies a

stop condition to end the operation and free the bus.

After a read of the CCR, the address remains at the

previous address +1 so the user can execute a current

address read of the CCR and continue reading the

next Register.

Table 1. Clock/Control Memory Map

Addr.

003F

0037

0036

0035

0034

0033

0032

0031

0030

0013

0012

0011

0010

Type

Status

RTC

(SRAM)

Control

(EEPROM)

Reg

Name

SSEC

DTR

ATR

INT

BAT

SS23

Y23

MIL

BP2

AL1

SS22

Y22

M22

S22

AL1E

BP1

AL0

SS21

Y21

D21

H21

M21

S21

ATR5

AL0E

BP0

Bit

(optional) Range

RWEL

WEL

RTCF

01h

SS20

SS13

SS12

SS11

SS10 0-99 xxh

DY2

DY1

DY0

0-6 xxh

Y20

Y13

Y12

Y11

Y10

0-99 xxh

G20

G13

G12

G11

G10

1-12 xxh

D20

D13

D12

D11

D10

1-31 xxh

H20

H13

H12

H11

H10

0-23 xxh

M20

M13

M12

M11

M10

0-59 xxh

S20

S13

S12

S11

S10

0-59 xxh

DTR2

DTR1

DTR0

00h

ATR4

ATR3

ATR2

ATR1

ATR0

00h

FO1

FO0 Read Only Read Only Read Only

00h

WD1

WD0 Read Only Read Only Read Only

18h

REV 1.1.30 3/24/04

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