X9252 Datasheet, PDF (6/21 Pages) Xicor Inc. – Quad Digitally-Controlled (XDCP) potentiometer

X9252
2-WIRE INTERFACE TIMING(S)
Symbol
f_SCL
t_HIGH
t_LOW
t_SU:STA
t_HD:STA
t_SU:STO
t_SU:DAT
t_HD:DAT
t_R⁽⁵⁾
t_F⁽⁵⁾
t_AA⁽⁵⁾
t_DH
t_IN⁽⁵⁾
t_BUF⁽⁵⁾
t_SU:WPA⁽⁵⁾
t_HD:WPA⁽⁵⁾
Parameter
Clock Frequency
Clock High Time
Clock Low Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
Pulse Width Suppression Time at SCL and SDA inputs
Bus Free Time (Prior to Any Transmission)
A0, A1, A2 and WP Setup Time
A0, A1, A2 and WP Hold Time
SDA vs. SCL Timing
t_F
t_HIGH
t_LOW
t_R
Min.
600
1300
600
600
600
100
30
0
1200
600
600
SCL
t_SU:STA
SDA
(Input Timing)
SDA
(Output Timing)
t_SU:DAT
t_HD:STA
t_HD:DAT
t_AA t_DH
WP, A0, A1, and A2 Pin Timing
START
SCL
Clk 1
STOP
SDA IN
WP, A0, A1, or A2
t_SU:WP
t_HD:WP
Max.
400
300
300
0.9
50
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
t_SU:STO
t_BUF
REV 1.4.1 7/29/03
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