X9252 Datasheet, PDF (16/21 Pages) Xicor Inc. – Quad Digitally-Controlled (XDCP) potentiometer

X9252
Byte Write Operation
For any Byte Write operation, the X9252 requires the
Slave Address byte, an Address Byte, and a Data Byte
(See Figure 6). After each of them, the X9252
responds with an ACK. The master then terminates the
transfer by generating a STOP condition. At this time, if
the write operation is to a volatile register (WCR, or
SR), the X9252 is ready for the next read or write
operation. If the write operation is to a nonvolatile
register (DR), and the WP pin is high, the X9252
begins the internal write cycle to the nonvolatile
memory. During the internal nonvolatile write cycle, the
X9252 does not respond to any requests from the
master. The SDA output is at high impedance.
The SR bits and WP pin determine the register being
accessed through the 2-wire interface. See Table 1 on
page 11.
As noted before, that any write operation to a Data
Register (DR), also writes to the WCR of the corre-
sponding DCP.
For example, to write 3Ahex to the Data Register 1 of
DCP2 the following sequence is required:
START
Slave Address
ACK
Address Byte
ACK
Data Byte
ACK
STOP
START
Slave Address
ACK
Address Byte
ACK
Data Byte
ACK
STOP
0101 0000 ^{(Hardware Address = 000,}
and a Write command)
0000 0111 (Indicates Status Register
address)
0000 0011 ^{(Data Register 1 and}
NVEnable selected)
0101 0000 (Hardware address = 000,
Write command)
0000 0010 (Access DCP2)
0011 1010 (Write Data Byte 3Ah)
During the sequence of this example, WP pin must be
high, and A0, A1, and A2 pins must be low. When com-
pleted, the DR21 register will be set to 3Ah, and also
the WCR2.
Figure 6. Byte Write Sequence
Signals from
the Master
Write
S
t
Slave
a
Address
r
Address
Byte
t
Data
S
Byte
t
o
p
Signal at SDA
01 01
0
Signals from
the Slave
A
A
A
C
C
C
K
K
K
REV 1.4.1 7/29/03
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