X9252 Datasheet, PDF (10/21 Pages) Xicor Inc. – Quad Digitally-Controlled (XDCP) potentiometer

X9252
PRINCIPLES OF OPERATION
The X9252 is an integrated circuit incorporating four
resistor arrays, their associated registers and counters,
and the serial interface logic providing direct communi-
cation between the host and the digitally controlled
potentiometers. This section provides detail description
of the following:
– Resistor Array
– Up/Down Interface
– 2-wire Interface
Resistor Array Description
The X9252 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (R_Hi and R_Li inputs). (See Figure 1.)
At both ends of each array and between each resistor
segment is a switch connected to the wiper (R_Wi) pin.
Figure 1. Detailed Block Diagram of one DCP
Within each individual array only one switch may be
turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select and enable one of 256 switches
(see Table 1). Note that each wiper has a dedicated
WCR. When all bits of a WCR are zeroes, the switch
closest to the corresponding R_L pin is selected. When
all bits of a WCR are ones, the switch closest to the
corresponding R_H pin is selected.
The WCR is volatile and may be written directly. There
are four non-volatile Data Registers(DR) associated
with each WCR. Each DR can be loaded into WCR. All
DRs and WCRs can be read or written.
Power Up and Down Requirements
During power up, CS must be high, to avoid inadvert-
ant “store” operations. At power up, the contents of
Data Registers DR00, DR10, DR20, and DR30, are
loaded into the corresponding wiper counter register.
i = 0, 1, 2, and 3
WCR[7:0] ²⁵⁵
Four
Non-Volatile
Data
Registers
DRi0, DRi1,
DRi2, and
DRi3
Volatile
8-bit
Wiper
Counter
Register
WCRi
= FF hex
254
253
R_Hi
252
One
of
256
Decoder
WP
SCL
SDA
Interface Control and
A2, A1, A0
Volatile Status Register (SR)
2
CS
(Shared by the Four DCPs)
U/D
1
DS1, DS0
WCR[7:0] 0
= 00 hex
R_Li
R_Wi
REV 1.4.1 7/29/03
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