X9252 Datasheet, PDF (14/21 Pages) Xicor Inc. – Quad Digitally-Controlled (XDCP) potentiometer

X9252
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to figure 4.). This byte
includes three parts:
– The four MSBs (SA7-SA4) are the Device Type
Identifier, which must always be set to 0101 in order
to select the X9252.
– The next three bits (SA3-SA1) are the Device
Address bits (AS2-AS0). To access any part of the
X9252’s memory, the value of bits AS2, AS1, and
AS0 must correspond to the logic levels at pins A2,
A1, and A0 respectively.
– The LSB (SA0) is the R/W bit. This bit defines the
operation to be performed on the device being
addressed. When the R/W bit is “1”, then a Read
operation is selected. A “0” selects a Write operation.
Figure 4. Slave Address (SA) Format
SA7 SA6 SA5 SA4 SA3 SA2 SA1 _SA0
0
1
0
1 AS2 AS1 AS0 R/W
Device Type
Identifier
Device
Address
Read or
Write
then no ACK is returned. If the high voltage cycle is
completed, an ACK is returned and the master can
then proceed with a new Read or Write operation.
(Refer to figure 5.)
Figure 5. Acknowledge Polling Sequence
Byte load completed by issuing
STOP. Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
NO
ACK returned?
YES
High Voltage
NO
complete. Continue command
sequence.
Slave Address
Bit(s)
SA7–SA4
SA3–SA1
SA0
Description
Device Type Identifier
Device Address
Read or Write Operation Select
YES
Continue normal Read or Write
command sequence
Issue STOP
PROCEED
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is
correctly issued (including the final STOP condition),
the X9252 initiates an internal high voltage write cycle.
This cycle typically requires 5 ms. During this time, any
Read or Write command is ignored by the X9252.
Write Acknowledge Polling is used to determine
whether a high voltage write cycle is completed.
During acknowledge polling, the master first issues a
START condition followed by a Slave Address Byte.
The Slave Address Byte contains the X9252’s Device
Type Identifier and Device Address. The LSB of the
Slave Address (R/W) can be set to either 1 or 0 in this
case. If the device is busy within the high voltage cycle,
2-WIRE SERIAL INTERFACE OPERATION
X9252 Digital Potentiometer Register Organization
Refer to the Functional Diagram on page 1. There are
four Digitally Controlled Potentiometers, referred to as
DCPi, i=0,1,2,3. Each potentiometer has one volatile
Wiper Control Register(WCR) with the corresponding
number, WCRi, i=0,1,2,3. Each potentiometer also has
four nonvolatile registers to store wiper position or
general data, these are numbered DRi0, DRi1, DRi2
and DRi3, i=0,1,2,3.
REV 1.4.1 7/29/03
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