X9252 Datasheet, PDF (17/21 Pages) Xicor Inc. – Quad Digitally-Controlled (XDCP) potentiometer

X9252
Page Write Operation
As stated previously, the memory is organized as a
single Status Register (SR), and four pages of four
registers each. Each page contains one Data Register
for each DCP. The order of the bytes within a page is
DR0i, followed by DR1i, followed by DR2i, and then
DR3i, with i being the Data Register number (0, 1, 2, or
3). Normally a page write operation will be used to
efficiently update all four data registers and WCR in a
single write command, starting at DCP0 and finishing
with DCP3.
In order to perform a Page Write operation to the mem-
ory array, the NVEnable bit in the SR must first be set
to “1”.
A Page Write operation is initiated in the same manner
as the byte write operation; but instead of terminating
the write cycle after the first data byte is transferred,
the master can transmit up to 4 bytes (See Figure 7).
After the receipt of each byte, the X9252 responds with
an ACK, and the internal DCP address counter is
incremented by one. The page address remains
Figure 7. Page Write Operation
constant. When the counter reaches the end of the
page (DR3i, 03hex), it “rolls over” and goes back to the
first byte of the same page (DR0i, 00hex).
For example, if the master writes 3 bytes to a page
starting at location DR22, the first 2 bytes are written to
locations DR22 and DR32, while the last byte is written
to locations DR02. Afterwards, the DCP counter would
point to location DR12. If the master supplies more
than 4 bytes of data, then new data overwrites the
previous data, one byte at a time.
The master terminates the loading of Data Bytes by
issuing a STOP condition, which initiates the
nonvolatile write cycle. As with the Byte Write
operation, all inputs are disabled until completion of the
internal write cycle. If the WP pin is high, the
nonvolatile write cycle doesn’t start and the bytes are
discarded.
Notice that the Data Bytes are also written to the WCR
of the corresponding DCPs, therefore in the above
example, WCR2, WCR3, and WCR0 are also written.
Signals from
the Master
Signal at SDA
Signals from
the Slave
Write
S
t
a
Slave
r
Address
t
01 01
0
A
C
K
Address
Byte
2<n<4
S
t
Data Byte (1)
Data Byte (n)
o
p
A
A
A
C
C
C
K
K
K
REV 1.4.1 7/29/03
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