X76F041 Datasheet, PDF (5/21 Pages) Xicor Inc. – PASS TM SecureFlash

X76F041
The retry register must have a higher value than the retry
counter for correct device operation. If the retry counter
value is larger than the retry register and the retry
counter is enabled, the device will wrap around allowing
up to an additional 255 incorrect access attempts.
If the Retry counter enable bit is a “0”, then the retry
counter is disabled.
Retry Register/Counter
Both the retry register and retry counter are accessible in
the configuration mode and may be programmed with a
value of 0 to 255.
The difference between the retry register and the retry
counter is the number of access attempts allowed, there-
fore the retry counter must be programmed to a smaller
value than the retry register to prevent wrap around.
Figure 4. Data Validity During Write
DEVICE PROTOCOL
The X76F041 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device as
the receiver. The device controlling the transfer is a mas-
ter and the device being controlled is the slave. The mas-
ter will always initiate data transfers, and provide the
clock for both transmit and receive operations. Therefore,
the X76F041 will be considered a slave in all applica-
tions.
Start Condition
All commands except for response to reset are preceded
by the start condition, which is a HIGH to LOW transition
of SDA when SCL is HIGH. The X76F041 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condition
has been met.
SCL
SDA
Figure 5. Definition of Start and Stop
DATA STABLE DATA
CHANGE
SCL
7002 ILL F07
SDA
START BIT
STOP BIT
7002 ILL F08
NOTE: The part requires the SCL input to be LOW during non-active periods of operation. In other words, the SCL will need to be LOW prior to
any START condition and LOW after a STOP condition. This is also reflected in the timing diagram.
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