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| X76F041 Datasheet, PDF (19/21 Pages) Xicor Inc. – PASS TM SecureFlash | |||
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X76F041
VCC to CS Setup Timing Diagram
VCC
CS
SCL
VCCMIN
tVCCS
tSU:SCL
tSU:CS
CS Deselect
CS
SDA (OUT)
from slave
tHZ2
RST Timing Diagram â Response to a Synchronous Reset (ISO)
RST
SCL
SDA
tRST
tNOL
1st
clk.
pulse
tPD
tSU:RST
tHIGH_RST
2nd
clk.
pulse
tPD
1st DATA BIT
fSCL_RST
tLOW_RST
3rd
clk.
pulse
2nd DATA BIT
7002 ILL F29
7002 ILL F29A
CS
(low)
7002 ILL F30
NOTES: (1) The reset operation results in an answer from the part containing a header transmitted from the part to the master. The header has a
ï¬xed length of 32 bits and begins with two mandatory ï¬elds of eight bits : H1 and H2.
(2) The chronological order of transmission of the information bits shall correspond to bit identiï¬cation b1 to b32 with the LEAST
signiï¬cant bit transmitted ï¬rst.
(3) The current values are:
H1 : 19 h
H2 : 55 h
H3 : AA h
H4 : 55 h
19
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