X76F041 Datasheet, PDF (4/21 Pages) Xicor Inc. – PASS TM SecureFlash

X76F041
Array Control
The four 1K arrays, are each programmable to different
levels of access and functionality. Each array can be pro-
grammed to require or not require the read/write pass-
words. The functional options are:
• Read and Write Access.
• Read access with all write operations locked out.
• Read access and program only (writing a “1” to a
“0”). If an attempt to change a “0” to a “1” occurs the
X76F041 will reset, issue a “no ACK” and enter the
standby power mode.
• No read or write access to the memory. Access only
through use of the configuration password.
Array Map
First ‘1k’
Second ‘1k’
Third ‘1k’
Fourth ‘1k’
Addresses 000
Addresses 080
Addresses 100
Addresses 180
07F (hex)
0FF (hex)
17F (hex)
1FF (hex)
High-order
Addresses
7002 ILL F04A
8 Bit Array Control Register 1
SECOND 1K
X2 Y2 Z2 T2
ACCESS
MSB
FUNCTION
FIRST 1K
X1 Y1 Z1 T1
ACCESS
FUNCTION
LSB
7002 ILL F05A
8 Bit Array Control Register 2
UPPER 1K
X4 Y4 Z4 T4
ACCESS
MSB
FUNCTION
THIRD 1K
X3 Y3 Z3 T3
ACCESS
FUNCTION
LSB
7002 ILL F05B
Functional Bits
Z
T
0
0
1
0
0
1
1
1
FUNCTIONALITY
READ AND WRITE UNLIMITED
READ ONLY, WRITE LIMITED
PROGRAM & READ ONLY,
ERASE LIMITED
NO READ OR WRITE, FULLY
LIMITED
7002 FRM T02
Access Bits
X
Y
READ
PASSWORD
WRITE
PASSWORD
0
0 NOT REQUIRED NOT REQUIRED
1
0 NOT REQUIRED REQUIRED
0
1 REQUIRED
NOT REQUIRED
1
1 REQUIRED
8-Bit Configuration Register
REQUIRED
7002 FRM T03
MSB
LSB
UA1 UA2 1
0 RCR RCE 0
0
RESERVED
RETRY COUNTER ENABLE
RETRY COUNTER RESET
RESERVED
RESERVED
UNAUTHORIZED ACCESS BIT 2
UNAUTHORIZED ACCESS BIT 1
7002 ILL F06
Unauthorized Access Bits (UA1, UA2):
10
Access is forbidden if retry register equals the retry
counter (provided that the retry counter is enabled) and
no further access of any kind will be allowed.
0 1, 0 0, 1 1
Only configuration operations are allowed if the retry reg-
ister equals the retry counter (provided that the retry
counter is enabled).
Retry Counter Reset Bit (RCR):
If the retry counter reset bit is a “1” then the retry counter
will be reset following a correct password, provided the
retry counter is enabled.
If the retry counter reset bit is a “0” then the retry counter
will not be reset following a correct password, provided
the retry counter is enabled.
Retry Counter Enable Bit (RCE):
If the Retry counter enable bit is a “1”, then the retry
counter is enabled. An initial comparison between the
retry register and retry counter determines whether the
number of allowed incorrect password attempts has
been reached. If not, the protocol continues and in case
of a wrong password, the retry counter is incremented by
one. If the password is correct then the retry counter will
either be reset or unchanged, depending on the reset bit.
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