X76F041 Datasheet, PDF (17/21 Pages) Xicor Inc. – PASS TM SecureFlash

X76F041
Bus Timing⁽¹⁾ — SDA Driven by the Bus Master
SCL
SDA (IN)
from master
tFSCL
tRSCL
tF
tR
Start
bit
tLOW
tSU:DAT
tHIGH
Bus Timing⁽²⁾ — SDA Driven by the Slave
tHD:DAT
7002 ILL F22
SCL
SDA (OUT)
from slave
1st clock
pulse of
sequence
tDV
tLZ
START Condition Timing
last clock
pulse of
sequence
tDH
tHZ1
7002 ILL F23
SCL
SDA (IN)
from master
tSTAS1
tSTAH1
tSTAS2
tSTAH2
Start Bit
7002 ILL F24
NOTES: (1) The master may issue a STOP condition at any given time in which it is driving the SDA line. In other words, when the part is sending
ACK or data the master may NOT issue a STOP condition. The part will not respond to any such attempt which also causes bus con-
tention. At any other time, a STOP condition will cause the part to reset and stop (enter a stand-by mode). Write operations will termi-
nate prior to entering the stand-by mode.
(2) When the part drives the SDA line, it will tri-state the bus only after the last bit of the sequence. In other words, after the 8th bit of a byte
that is read or after ACK between incoming bytes. In all other cases when the part drives the bus (between successive bits) it will con-
tinue to drive the bus also during the clock LOW periods.
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