X68C64 Datasheet, PDF (5/12 Pages) Xicor Inc. – E2 Micro-Peripheral

X68C64
Toggle Bit Polling
Because the X68C64 typical nonvolatile write cycle time
is less than the specified 5ms, Toggle Bit Polling has
been provided to determine the early completion of
write. During the internal programming cycle, I/O₆ will
toggle from HIGH to LOW and LOW to HIGH on subse-
quent attempts to read the device. When the internal
Toggle Bit Polling E Control
cycle is complete, the toggling will cease and the device
will be accessible for additional read or write operations.
Due to the dual plane architecture, reads for polling must
occur in the plane that is being written; that is, the state
of A₁₂ during a write must match the state of A₁₂ during
Toggle Bit Polling.
OPERATION
CE
LAST BYTE
WRITTEN
I/O6=X
I/O6=X
I/O6=X
I/O6=X
X68C64 READY FOR
NEXT OPERATION
AS
A/D0–A/D7
AIN DIN
AIN DOUT
AIN DOUT
AIN DOUT
AIN DOUT
AIN
A8–A12
A12=n
A12=n
A12=n
A12=n
A12=n
ADDR
E
R/W
3868 FHD F08
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
5