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X68C64 Datasheet, PDF (3/12 Pages) Xicor Inc. – E2 Micro-Peripheral
X68C64
PRINCIPLES OF OPERATION
The X68C64 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The
X68C64 provides 8K bytes of E2PROM which can be
used either for Program Storage, Data Storage, or a
combination of both in systems based upon Von
Neumann (68XX) architectures. The X68C64 incorpo-
rates the interface circuitry normally needed to decode
the control signals and demultiplex the Address/Data
bus to provide a “Seamless” interface.
The interface inputs on the X68C64 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip
microcontroller.
The X68C64 is internally organized as two independent
planes of 4K bytes of memory with the A12 input select-
ing which of the two planes of memory are to be
accessed. While the processor is executing code out of
one plane, write operations can take place in the other
plane, allowing the processor to continue execution of
code out of the X68C64 during a byte or page write to the
device.
The X68C64 also features an advanced implementation
of the Software Data Protection scheme, called Block
Protect, which allows the device to be broken into 8
independent sections of 1K bytes. Each of these sec-
tions can be independently enabled for write operations;
thereby allowing certain sections of the device to be
secured so that updates can only occur in a controlled
environment (e.g. in an automotive application, only at
an authorized service center). The desired set-up con-
figuration is stored in a nonvolatile register, ensuring the
configuration data will be maintained after the device is
powered down.
The X68C64 also features a Write Control input (WC),
which serves as an external control over the completion
of a previously initiated page load cycle.
The X68C64 also features the industry standard
E2PROM characteristics such a byte or page mode
write and Toggle Bit Polling.
DEVICE OPERATION
Motorola 68XX operation requires the microcontroller’s
AS, E, and R/W outputs tied to the X68C64 AS, E, and
R/W inputs respectively.
The falling edge of AS will latch the addresses for both
a read and write operation. The state of R/W output
determines the operation to be performed, with the E
signal acting as a data strobe.
If R/W is HIGH and CE HIGH (read operation), data will
be output on A/D0–A/D7 after E transitions HIGH. If
R/W is LOW and CE is HIGH (write operation), data
presented at A/D0–A/D7 will be strobed into the X68C64
on the HIGH to LOW transition of E.
Typical Application
30
XTAL
8 MHz
OSC.
29
8
EXTAL
VCC VCC
25 MODA
24 MODB
PC0 31
PC1 32
PC2 33
PC3 34
PC4 35
PC5 36
PC6 37
PC7 38
PB0 16
PB1 15
PB2 14
PB3 13
PB4 12
PB7 9
AS 26
E 27
R/W 28
68HC11A8
24
7 A/D0 VCC
8 A/D1
9 A/D2
10 A/D3
11 A/D4
13 A/D5
14 A/D6
15 A/D7
21 A8
20 A9
17 A10
19 A11
2 A12
16 CE
5 WC
22 AS
18 E
23 R/W
6 SEL
VSS
X68C64 12
3868 ILL F03.2
3