X68C64 Datasheet, PDF (4/12 Pages) Xicor Inc. – E2 Micro-Peripheral

X68C64
MODE SELECTION
CE
E
R/W
Mode
I/O
Power
VSS
LOW
HIGH
HIGH
X
X
HIGH
X
X
HIGH
LOW
Standby
Standby
Read
Write
High Z
High Z
D_OUT
DIN
Standby (CMOS)
Standby (TTL)
Active
Active
3868 PGM T02.1
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X68C64
supports page mode write operations. This allows the
microcontroller to write from one to thirty-two bytes of
data to the X68C64. Each individual write within a page
write operation must conform to the byte write timing
requirements. The rising edge of E starts a timer delay-
ing the internal programming cycle 100µs. Therefore,
each successive write operation must begin within 100µs
of the last byte written. The following waveforms illus-
trate the sequence and timing requirements.
Page Write Timing Sequence for E Controlled Operation
OPERATION
CE
BYTE 0
BYTE 1
BYTE 2
LAST BYTE
READ (1)(2)
AFTER tWC READY FOR
NEXT WRITE OPERATION
AS
A/D0–A/D7
A8–A12
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=x
AIN
ADDR
AIN
Next Address
E
R/W
tBLC
tWC
3868 FHD F07
Notes: (1) For each successive write within a page write cycle A₅–A₁₂ must be the same.
(2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page
write operation. Two responses are possible.
a. Reading from the same plane being written (A₁₂ of Read = A₁₂ of Write) is effectively a Toggle Bit Polling operation.
b. Reading from the opposite plane being written (A₁₂ of Read ≠ A₁₂ of Write) true data will be returned, facilitating the use of a
single memory component as both program and data storage.
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