X3100 Datasheet, PDF (12/40 Pages) Xicor Inc. – 3 or 4 Cell Li-Ion Battery Protection and Monitor IC

X3100/X3101 – Preliminary Information
Bit 1 of the status register simply indicates whether or
not the X3100 or X3101 is in over-discharge protection
mode.
Bit 2 of the status register (CCES+OVDS) indicates the
status of two conditions of the X3100 or X3101. Cell
Charge Enable Status (CCES) is an internally generated
signal which indicates the status of any cell voltage
(V_CELL) with respect to the Cell Charge Enable Voltage
(V_CE). Over-charge Voltage Detection Status (OVDS) is
an internally generated signal which indicates whether
Table 18. Status Register Functionality.
or not the X3100 or X3101 is in over-charge protection
mode.
When the cell charge enable function is switched ON
(configuration bit SWCEN=0), the signals CCES and
OVDS are logically OR’ed (CCES+OVDS) and written to
bit 2 of the status register. If the cell charge enable
function is switched OFF (configuration bit SWCEN=1),
then bit 2 of the status register effectively only represents
information about the over-charge status (OVDS) of the
X3100 or X3101 (See Table 18, Table 17 and Figure 2).
Bit(s) Name
Description
Case Status
Interpretation
Voltage regulator
status
0 VRGS+OCDS
+
-
Over-current
detection status
1 ^{VRGO not yet tuned (VRGO=5V ± 10%) OR}
X3100/X3101 in over-current protection mode.
0 ^{VRGO tuned (VRGO=5V ± 0.5%) AND}
X3100/X3101 NOT in over-current protection mode.
1
UVDS
Over-discharge
detection status
-
1 X3100/X3101 in over-discharge protection mode
0 X3100/X3101 NOT in over-discharge protection mode
1 ^{VCELL < VCE OR}
Cell charge
enable status
SWCEN =0^†
2 CCES+OVDS
+
0
X3100/X3101 in over-charge protection mode
V_CELL > V_CE AND
X3100/X3101 NOT in over-charge protection mode
Over-charge
detection status _{SWCEN =1â€} 
1
X3100/X3101 in over-charge protection mode
0 X3100/X3101 NOT in over-charge protection mode
3–7
-
-
0 Not used (always return zero)
Notes: ^† This bit is set in the configuration register.
X3100/X3101 INTERNAL PROTECTION FUNCTIONS
The X3100 and the X3101 provide periodic monitoring
(see section “Periodic Protection Monitoring” on page
12) for over-charge and over-discharge states and
continuous monitoring for an over-current state. It has
automatic shutdown when a protection mode is
encountered, as well as automatic return after the
device is released from a protection mode. When
sampling voltages through the analog port (Monitor
Mode), over-charge and over-discharge protection
monitoring is also performed on a continuous basis.
Voltage thresholds for each of these protection modes
(V_OV, V_UV, and V_OC respectively) can be individually
selected via software and stored in an internal non-
volatile register. This feature allows the user to avoid the
restrictions of mask programmed voltage thresholds, and
is especially useful during prototype/evaluation design
stages or when cells with slightly different
characteristics are used in an existing design.
Delay times for the detection of, and release from
protection modes (T_OV, T_UV/T_UVR, and T_OC/T_OCR
respectively) can be individually varied by setting the
values of external capacitors connected to pins OVT,
UVT, OCT.
Periodic Protection Monitoring
In normal operation, the analog select pins are set such
that AS2=L, AS1=L, AS0=L. In this mode the X3100 and
X3101 conserve power by sampling the cells for over or
over-discharge conditions.
In this state over-charge and over-discharge protection
circuitry are usually off, but are periodically switched on
by the internal Protection Sample Rate Timer (PSRT). The
REV 1.1.8 12/10/02
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Characteristics subject to change without notice. 12 of 40