X3100 Datasheet, PDF (10/40 Pages) Xicor Inc. – 3 or 4 Cell Li-Ion Battery Protection and Monitor IC

X3100/X3101 – Preliminary Information
Figure 4. Writing to Configuration Register
Power Up
Data Recalled
from Shadow
EEPROM to SRAM
Configuration Register
(SRAM=Old Value)
WCFIG (New Value)
Configuration Register
(Sram=New Value)
Store
NO
(New Value)
YES
in Shadow
EEPROM
Power Down
Power Up
WREN
Write
Enable
Data Recalled
from Shadow
EEPROM to SRAM
EEWRITE
Write to
4kbit EEPROM
Configuration Register
(SRAM=old value)
Power Down
Power Up
Data Recalled
from Shadow
EEPROM to SRAM
Configuration Register
(SRAM=New Value)
CONTROL REGISTER
The Control Register is realized as two bytes of volatile
RAM (Table 10, Table 11). This register is written using
the WCNTR instruction, see Table 30 and section “X3100/
X3101 SPI Serial Communication” on page 22.
Table 10. Control Register—Upper Byte
15 14 13 12 11 10 9
8
CBC4 CBC3 CBC2 CBC1 UVPC OVPC CSG1 CSG0
Table 11. Control Register—Lower Byte
7
6
5
4
3
2
1
0
SLP
0
0
x
x
x
x
x
Since the control register is volatile, data will be lost
following a power down and power up sequence. The
default value of the control register on initial power up
or when exiting the SLEEP MODE is 00h (for both
upper and lower bytes respectively). The functions that
can be manipulated by the Control Register are shown
in Table 12.
Table 12. Control Register Functionality
Bit(s) Name
Function
0-4
– (don’t care)
5,6 0, 0 Reserved—write 0 to these locations.
7
SLP Select sleep mode.
8,9
CSG1,
CSG0
Select current sense voltage gain
10 OVPC OVP control: switch pin OVP = V_CC/V_SS
11 UVPC UVP control: switch pin UVP = V_CC/V_SS
12 CBC1 CB1 control: switch pin CB1 = V_CC/V_SS
13 CBC2 CB2 control: switch pin CB2 = V_CC/V_SS
14 CBC3 CB3 control: switch pin CB3 = V_CC/V_SS
15 CBC4 CB4 control: switch pin CB4 = V_CC/V_SS
Sleep Control (SLP)
Setting the SLP bit to ‘1’ forces the X3100 or X3101 into
the sleep mode, if V_CC < V_SLP. See section “Sleep
Mode” on page 15.
Table 13. Sleep Mode Selection
Control Register Bits
SLP
Operation
0
Normal operation mode
1
Device enters Sleep mode
REV 1.1.8 12/10/02
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Characteristics subject to change without notice. 10 of 40