WM8948 Datasheet, PDF (88/189 Pages) Wolfson Microelectronics plc – Stereo Low-Power CODEC with Video Buffer and Touch Panel Controller

WM8948
Production Data
The resistance RREF is a function of the circuit gain and a function of the parallel combination of
RSOURCE and RLOAD. When VB_GAIN = 0 (0dB gain), the current gain of the video buffer is 5, as
described by the equation IVBOUT = 5 x IVBREF.
The resistor RREF should be set equal to 5 x (RSOURCE // RLOAD), where (RSOURCE // RLOAD) is the
effective resistance of the parallel combination of RSOURCE and RLOAD. (Note that the required
resistance RREF is the same for both settings of VB_GAIN.)
In a typical application, RLOAD = 75Ω, RSOURCE = 75Ω, RREF = 187Ω.
RECOMMENDED VIDEO BUFFER INITIALISATION SEQUENCE
Power Up (Video signal AC coupled to Video Buffer input):
ACTION
Turn on external supplies and wait for
the supply voltages to settle.
Reset registers to default state (software
reset)
Enable VMID Fast Start and Start up
Bias
Select Start-Up Bias and set VMID soft
start for start-up ramp
If using VMID as the reference voltage
for the LDO then select VMID fast start
or set to 0 if using the Bandgap as the
reference voltage for LDO.
Select LDO Start-Up Bias and enable
LDO
Delay 300ms for LDO to settle
Enable VMID Buffer and Master Bias
Set VMID_SEL[1:0] for fast start-up
Enable VMID
Delay 150ms to allow VMID to settle
Set LDO for normal operation
Set VMID for normal operation
Set VMID divider for normal operation
Enable VMID
Delay 150ms to allow VMID to settle
Set LDO for normal operation
Set Video Buffer Gain as required
Set Video Buffer Filter Q Boost as
required
Enable Video Buffer Clamp
Enable Video Buffer Pulldown
Enable video buffer
Delay 20ms for buffer to capture input
level
Disable Video Buffer Pulldown
LABEL
SW_RESET
VMID_FAST_START = 1
STARTUP_BIAS_ENA = 1
BIAS_SRC = 1
VMID_RAMP[1:0] = 01
LDO_REF_SEL_FAST = 1
LDO_BIAS_SRC = 1
LDO_ENA = 1
BIAS_ENA = 1
VMID_BUF_ENA = 1
VMID_SEL[1:0] = 11
VMID_ENA = 1
LDO_REF_SEL_FAST = 0
LDO_BIAS_SRC = 0
VMID_FAST_START = 0
STARTUP_BIAS_ENA = 0
VMID_SEL = 01
VMID_ENA = 1
LDO_REF_SEL_FAST = 0
LDO_BIAS_SRC = 0
VB_GAIN
VB_QBOOST
VB_CLAMP = 1
VB_PD = 1
VB_ENA = 1
VB_PD = 0
REGISTER[BITS]
R0 (00h) [15:0]
R7 (07h) [11]
R7 (07h) [8]
R7 (07h) [7]
R7 (07h) [6:5]
R53 (35h) [14]
R53 (35h) [5]
R53 (35h) [15]
R2 (02h) [3]
R2 (02h) [2]
R2 (02h) [1:0]
R7 (07h) [4]
R53 (35h) [14]
R53 (35h) [5]
R7 (07h) [11]
R7 (07h) [8]
R2 (02h) [1:0]
R7 (07h) [4]
R53 (35h) [14]
R53 (35h) [5]
R38 (26h) [5]
R38 (26h) [6]
R38 (26h) [0]
R38 (26h) [1]
R38 (26h) [7]
R38 (26h) [1]
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PD, May 2011, Rev 4.1
88