WM8948 Datasheet, PDF (112/189 Pages) Wolfson Microelectronics plc – Stereo Low-Power CODEC with Video Buffer and Touch Panel Controller

WM8948
Production Data
Figure 50 Power On Reset timing - DCVDD Enabled First
The P¯ ¯O¯R signal is undefined until LDOVDD has exceeded the minimum threshold, Vpora Once this
threshold has been exceeded, P¯ ¯O¯R is asserted low and the chip is held in reset. In this condition, all
writes to the control interface are ignored. Once LDOVDD and DCVDD have both reached their
respective power on thresholds, P¯ ¯O¯R is released high, all registers are in their default state, and
writes to the control interface may take place.
Note that a minimum power-on reset period, TPOR, applies even if LDOVDD and DCVDD have zero
rise time. (This specification is guaranteed by design rather than test.)
On power down, P¯ ¯O¯R is asserted low when LDOVDD or DCVDD falls below their respective power-
down thresholds.
Typical Power-On Reset parameters for the WM8948 are defined in Table 71.
SYMBOL
DESCRIPTION
Vpora
Vpora_on
Vpora_off
Vpord_on
Power-On undefined threshold (LDOVDD)
Power-On threshold (LDOVDD)
Power-Off threshold (LDOVDD)
Power-On threshold (DCVDD)
Vpord_off
TPOR
Power-Off threshold (DCVDD)
Minimum Power-On Reset period
Table 71 Typical Power-On Reset Parameters
MIN
TYP
MAX UNIT
0.5
V
1.15
V
1.12
V
0.57
V
0.56
V
10.6
μs
Separate Power-On Reset circuits are also implemented on the DBVDD and SPKVDD domains.
These circuits ensure correct device behaviour whenever these supplies are enabled or disabled.
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PD, May 2011, Rev 4.1
112