WM8948 Datasheet, PDF (163/189 Pages) Wolfson Microelectronics plc – Stereo Low-Power CODEC with Video Buffer and Touch Panel Controller

Production Data
REGISTER BIT
ADDRESS
R95 (5Fh) 15:0
SE1_DF1_L
2
LABEL
SE1_DF1_L2
[15:0]
Register 5Fh SE1_DF1_L2
DEFAULT
DESCRIPTION
0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) left
_0000_000 channel DF1 filter
0
WM8948
REFER TO
REGISTER BIT
ADDRESS
R96 (60h) 15:0
SE1_DF1_R
0
LABEL
SE1_DF1_R0
[15:0]
Register 60h SE1_DF1_R0
DEFAULT
DESCRIPTION
0001_0000 Filter coefficients for Signal Enhancement 1 (SE1) right
_0000_000 channel DF1 filter
0
REFER TO
REGISTER BIT
ADDRESS
R97 (61h) 15:0
SE1_DF1_R
1
LABEL
SE1_DF1_R1
[15:0]
Register 61h SE1_DF1_R1
DEFAULT
DESCRIPTION
0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) right
_0000_000 channel DF1 filter
0
REFER TO
REGISTER BIT
ADDRESS
R98 (62h) 15:0
SE1_DF1_R
2
LABEL
SE1_DF1_R2
[15:0]
Register 62h SE1_DF1_R2
DEFAULT
DESCRIPTION
0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) right
_0000_000 channel DF1 filter
0
REFER TO
REGISTER BIT
LABEL
DEFAULT
DESCRIPTION
ADDRESS
R100 (64h)
1
SE2_RETUNE
SE2_RETU
_R_ENA
NE_CONFI
G
0 SE2_RETUNE
_L_ENA
0
SE2 Right channel ReTune™ filter enable
0 = Disabled
1 = Enabled
0
SE2 Left channel ReTune™ filter enable
0 = Disabled
1 = Enabled
Register 64h SE2_RETUNE_CONFIG
REFER TO
REGISTER
ADDRESS
R101 (65h)
SE2_RETU
NE_C0
BIT
15:0
LABEL
DEFAULT
DESCRIPTION
SE2_RETUNE 0001_0000 Filter coefficients for Signal Enhancement 2 (SE2)
_C0[15:0] _0000_000 ReTune™ filter
0
Register 65h SE2_RETUNE_C0
REFER TO
w
PD, May 2011, Rev 4.1
163