WM8351 Datasheet, PDF (204/330 Pages) Wolfson Microelectronics plc – Wolfson AudioPlus™ Stereo CODEC with Power Management

WM8351
Production Data
24.3.7 AUXADC AND DIGITAL COMPARATOR INTERRUPTS
The first-level AUXADC_INT interrupt comprises several second-level interrupts for the auxiliary ADC
and associated digital comparators. Each of these has a status bit in Register R26 and a mask bit in
Register R34, as defined in Table 149.
ADDRESS
BIT
LABEL
R26 (1Ah)
8
AUXADC_DATARDY_EINT
Interrupt Status
2
7
AUXADC_DCOMP4_EINT
6
AUXADC_DCOMP3_EINT
5
AUXADC_DCOMP2_EINT
4
AUXADC_DCOMP1_EINT
R34 (22h)
8:4 “IM_” + name of respective bit
Interrupt Status
in R26
2 Mask
Table 149 AUXADC Interrupts
DESCRIPTION
Auxiliary data ready.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCOMP4 interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCOMP3 interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCOMP2 interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCOMP1 interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R34 enables or masks the
corresponding bit in R26. The default
value for these bits is 0 (unmasked).
24.3.8 RTC INTERRUPTS
The first-level RTC_INT interrupt comprises three second-level interrupts for the Real Time Clock.
Each of these has a status bit in Register R25 and a mask bit in Register R33, as defined in Table
150.
ADDRESS
R25 (19h)
Interrupt Status
1
BIT
LABEL
7
RTC_PER_EINT
6
RTC_SEC_EINT
5
RTC_ALM_EINT
R33 (21h)
7:5 “IM_” + name of respective bit
Interrupt Status
in R25
1 Mask
Table 150 RTC Interrupts
DESCRIPTION
RTC periodic interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
RTC 1s rollover complete (1Hz tick).
(Rising Edge triggered)
Note: This bit is cleared once read.
RTC alarm signalled.
(Rising Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R33 enables or masks the
corresponding bit in R25. The default
value for these bits is 0 (unmasked).
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PD, April 2012, Rev 4.5
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