WM8994 Datasheet, PDF (182/359 Pages) Wolfson Microelectronics plc – Multi-Channel Audio Hub CODEC for Smartphones

WM8994
Production Data
REGISTER
ADDRESS
BIT
LABEL DEFAULT
14 AIF2DACR_
1
SRC
13 AIF2DAC_T
0
DM
12 AIF2DAC_T
0
DM_CHAN
11:10 AIF2DAC_B
00
OOST [1:0]
R790 (0316h) 1 AIF2DACL_
0
AIF2 DAC
DAT_INV
Data
0 AIF2DACR_
0
DAT_INV
R791 (0317h) 1 AIF2ADCL_
0
AIF2 ADC
DAT_INV
Data
0 AIF2ADCR_
0
DAT_INV
Table 98 AIF2 Digital Audio Data Control
DESCRIPTION
AIF2 Right Receive Data Source Select
0 = Right DAC receives left interface data
1 = Right DAC receives right interface data
AIF2 receive (DAC) TDM Enable
0 = Normal DACDAT2 operation
1 = TDM enabled on DACDAT2
AIF2 receive (DAC) TDM Slot Select
0 = Slot 0
1 = Slot 1
AIF2 Input Path Boost
00 = 0dB
01 = +6dB (input must not exceed -6dBFS)
10 = +12dB (input must not exceed -12dBFS)
11 = +18dB (input must not exceed -18dBFS)
AIF2 Left Receive Data Invert
0 = Not inverted
1 = Inverted
AIF2 Right Receive Data Invert
0 = Not inverted
1 = Inverted
AIF2 Left Transmit Data Invert
0 = Not inverted
1 = Inverted
AIF2 Right Transmit Data Invert
0 = Not inverted
1 = Inverted
AIF2 - MONO MODE
AIF2 can be configured to operate in mono DSP mode by setting AIF2_MONO = 1 as described in
Table 99. Note that mono mode is only supported in DSP mode, ie when AIF2_FMT = 11.
In mono mode, the Left channel data or the Right channel data may be selected for output on
ADCDAT2. The selected channel is determined by the AIF2ADCL_ENA and AIF2ADCR_ENA bits. (If
both bits are set, then the Right channel data is selected.)
In mono mode, the DACDAT2 input can be enabled on the Left and/or Right signal paths using the
AIF2DACL_ENA and AIF2DACR_ENA bits. The mono input can be enabled on both paths at the
same time if required.
In mono mode, the number of BCLK cycles per LRCLK frame must be less than double the AIF2 word
length. This requires AIF2DAC_RATE to be less than double the value selected by the AIF2_WL
register. When the GPIO6 pin is configured as ADCLRCLK2, then AIF2ADC_RATE must also be less
than double the value selected by the AIF2_WL register. See Table 89 for details of the
AIF2DAC_RATE and AIF2ADC_RATE registers.
REGISTER BIT
ADDRESS
LABEL
R785 (0311h) 8 AIF2_MONO
AIF2 Control
(2)
Table 99 AIF2 Mono Mode Control
DEFAULT
0
DESCRIPTION
AIF2 DSP Mono Mode
0 = Disabled
1 = Enabled
Note that Mono Mode is only supported when
AIF2_FMT = 11. The number of BCLK cycles
per LRCLK frame must be less the 2 x AIF2
Word Length.
w
PD, April 2012, Rev 4.4
182