WM8994 Datasheet, PDF (169/359 Pages) Wolfson Microelectronics plc – Multi-Channel Audio Hub CODEC for Smartphones

Production Data
WM8994
DIGITAL AUDIO INTERFACE CONTROL
This section describes the configuration of the WM8994 digital audio interface paths.
Interfaces AIF1 and AIF2 can be configured as Master or Slave, or can be tri-stated. Each input and
output signal path can be independently enabled or disabled. AIF output (digital record) and AIF input
(digital playback) paths can use a common Left/Right clock, or can use separate clocks for mixed
sample rates.
Interfaces AIF1 and AIF2 each support flexible formats, word-length, TDM configuration, channel
swapping and input path digital boost functions. 8-bit companding modes and digital loopback is also
possible.
A third interface, AIF3, is partially supported, using multiplexers to re-configure alternate connections
to AIF1 or AIF2. Note that AIF3 operates in Master mode only.
AIF1 - MASTER / SLAVE AND TRI-STATE CONTROL
The Digital Audio Interface AIF1 can operate in Master or Slave modes, selected by AIF1_MSTR. In
Master mode, the BCLK1 and LRCLK1 signals are generated by the WM8994 when one or more
AIF1 channels is enabled.
When AIF1_LRCLK_FRC or AIF1_CLK_FRC is set in Master mode, then LRCLK1 and ADCLRCLK1
are output at all times, including when none of the AIF1 audio channels is enabled. Note that LRCLK1
and ADCLRCLK1 are derived from BCLK1, and either an internal or external BCLK1 signal must also
be present to generate LRCLK1 or ADCLRCLK1.
When AIF1_CLK_FRC is set in Master mode, then BCLK1 is output at all times, including when none
of the AIF1 audio channels is enabled.
The AIF1 interface can be tri-stated by setting the AIF1_TRI register. When this bit is set, then all of
the AIF1 outputs are un-driven (high-impedance). Note that the ADCLRCLK1/GPIO1 pin is a
configurable pin which may take different functions independent of AIF1. The AIF1_TRI register only
controls the ADCLRCLK1/GPIO1 pin when its function is set to ADCLRCLK1. See “General Purpose
Input/Output” to configure the GPIO1 pin.
REGISTER BIT
ADDRESS
LABEL DEFAULT
DESCRIPTION
R770 (0302h) 15 AIF1_TRI
AIF1
Master/Slave
0
AIF1 Audio Interface tri-state
0 = AIF1 pins operate normally
1 = Tri-state all AIF1 interface pins
Note that the GPIO1 pin is controlled by this
register only when configured as
ADCLRCLK1.
14 AIF1_MSTR
0
AIF1 Audio Interface Master Mode Select
0 = Slave mode
1 = Master mode
13 AIF1_CLK_F
0
RC
Forces BCLK1, LRCLK1 and ADCLRCLK1 to
be enabled when all AIF1 audio channels are
disabled.
0 = Normal
1 = BCLK1, LRCLK1 and ADCLRCLK1
always enabled in Master mode
12 AIF1_LRCL
K_FRC
0
Forces LRCLK1 and ADCLRCLK1 to be
enabled when all AIF1 audio channels are
disabled.
0 = Normal
1 = LRCLK1 and ADCLRCLK1 always
enabled in Master mode
Table 87 AIF1 Master / Slave and Tri-state Control
w
PD, April 2012, Rev 4.4
169