W741L250 Datasheet, PDF (9/86 Pages) Winbond – 4-BIT MICROCONTROLLER

W741L250
Divider 0
Divider 0 is organized as a 14-bit binary up-counter designed to generate periodic interrupts, as
shown in Figure 4. When the system starts, the divider is incremented by each system clock (FOSC).
When an overflow occurs, the divider event flag is set to 1 (EVF.0 = 1). Then, if the divider interrupt
enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag
has been set (HEF.0 = 1), the hold state is terminated. In addition, the 4 MSB of the divider can be
reset by executing the CLR DIVR0 instruction.
Watchdog Timer (WDT)
The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program
from unknown errors. The WDT is enable when the corresponding option code bit of the WDT is set
to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is
FOSC/1024. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/1024) by executing
the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the
instruction CLR WDT. In normal operation, the application program must reset WDT before it
overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset.
The WDT minimun overflow period is 468.75 mS when the system clock (FOSC) is 32 KHz and WDT
clock input is FOSC/1024. When the corresponding option code bit of the WDT is set to 0, the WDT
function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 4.
Fosc
Divider0
... Q1 Q2
Q9 Q10 Q11 Q12 Q13 Q14
RRRR
S
EVF.0
Q
R
HEF.0
IEF.0
Hold mode release (HCF.0)
Divider0 interrupt (INT0)
PMF.3
Fosc/16384
Fosc/1024
Enable
/Disable
Mask Option
1. Reset
2. CLR EVF, #01H
3. CLR DIVR0
WDT
Overflow signal
Qw1 Qw2 Qw3 Qw4
R
R
R
R
System Reset
1. Reset
2. CLR WDT
Figure 4. Organization of Divider 0 and Watchdog Timer
Timer/Counter
1. Timer 0 (TM0)
Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into
TM0 by executing the MOV TM0L (TM0H), R or MOV TM0, #I instructions. When the MOV TM0L
(TM0H), R instructions are executed, the TM0 will stop down-counting (if the TM0 is down-counting),
the MR0.3 will be reset to 0, and the specified value is loaded into TM0. If MR0.3 is set to 1, the
event flag 1 (EVF.1) is reset and the TM0 starts to count. When it decrements to FFH, Timer 0 stops
operating and generates an underflow (EVF.1 = 1). The interrupt is executed if the Timer 0 interrupt
enable flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1
has been set (HEF.1 = 1). The Timer 0 clock input can be set as FOSC/1024 or FOSC/4 by setting
Publication Release Date: March 1998
-9-
Revision A2