W741L250 Datasheet, PDF (16/86 Pages) Winbond – 4-BIT MICROCONTROLLER

W741L250
Port Enable Flag (PEF)
The port enable flag is organized as a 4-bit binary register (PEF.0 to PEF.3). Before port RC may be
used to release the hold mode or perform an interrupt function, the content of the PEF must be set
first. The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:
3210
PEF w w w w
Note: W means write only.
PEF.0: Enable/disable the signal change on pin RC.0 to release hold mode or perform interrupt.
PEF.1: Enable/disable the signal change on pin RC.1 to release hold mode or perform interrupt.
PEF.2: Enable/disable the signal change on pin RC.2 to release hold mode or perform interrupt.
PEF.3: Enable/disable the signal change on pin RC.3 to release hold mode or perform interrupt.
Stop Mode Wake-up Enable Flag for Port RC (SEF)
The stop mode wake-up flag for port RC is organized as a 4-bit binary register (SEF.0 to SEF.3).
Before port RC may be used to make the device exit the stop mode, the content of the SEF must be
set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows:
3210
SEF w w w w
Note: W means write only.
SEF 0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0.
SEF 1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1.
SEF 2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2.
SEF 3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.3.
Hold Mode Release Condition Flag (HCF)
The hold mode release condition flag is organized as an 8-bit binary register (HCF0 to HCF7). It
indicates by which interrupt source the hold mode has been released, and it is loaded by hardware.
The HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the
HCF bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be
reset by the CLR EVF, #I (EVF.n = 0) or MOV HEF, #I (HEF.n = 0) instructions. When EVF or HEF
has been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as
follows:
76543210
HCF
RR
RRR
Note: R means read only.
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