W741L250 Datasheet, PDF (6/86 Pages) Winbond – 4-BIT MICROCONTROLLER

W741L250
FUNCTIONAL DESCRIPTION
Program Counter (PC)
Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses
of the 2048 × 16 on-chip ROM containing the program instruction words. When jump or subroutine
call instructions or interrupt or initial reset conditions are to be executed, the address corresponding to
the instruction will be loaded into the program counter. The format used is shown below.
ITEM
ADDRESS INTERRUPT PRIORITY
Initial Reset
000H
-
INT 0 (Divider 0)
004H
1st
INT 1 (Timer 0)
008H
2nd
INT 2 (Port RC)
00CH
3rd
INT 4 ( _INT pin)
014H
4th
INT 7 (Timer 1)
020H
5th
JP Instruction
XXXH
-
Subroutine Call
XXXH
-
Stack Register (STACK)
The stack register is organized as 11 bits × 8 levels (first-in, last-out). When either a call subroutine or
an interrupt is executed, the program counter will be pushed onto the stack register automatically. At
the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed
to pop the contents of the stack register into the program counter. When the stack register is pushed
over the eighth level, the contents of the first level will be lost. In other words, the stack register is
always eight levels deep.
Program Memory (ROM)
The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 2048
× 4 bits. The first three quarters of ROM (000H to 5FFH) are used to store instruction codes only, but
the last quarter (600H to 7FFH) can store both instruction codes and the look-up table. Each look-up
table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements.
There are two registers (TABL and TABH) to be used in look-up table addressing and they are
controlled by MOV TABH, R and MOV TABL, R instructions. When the instruction MOVC R is
executed, the contents of the look-up table location address specified by TABH, TABL and ACC will
be read and transfered to the data RAM. Refer to the instruction table for more details. The
organization of the program memory is shown in Figure 1.
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