W741L250 Datasheet, PDF (15/86 Pages) Winbond – 4-BIT MICROCONTROLLER

W741L250
Hold Mode Release Enable Flag (HEF)
The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The
HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I
instruction. The bit descriptions are as follows:
76543210
HEF w
w
www
Note: W means write only.
HEF.0 = 1 Overflow from Divider 0 causes hold mode to be released.
HEF.1 = 1 Underflow from Timer 0 causes hold mode to be released.
HEF.2 = 1 Signal change at port RC causes hold mode to be released.
HEF.3 Reserved
HEF.4 = 1 Falling edge signal at the INT pin causes hold mode to be released.
HEF.5 & HEF.6 are reserved.
HEF.7 = 1 Underflow from Timer 1 causes hold mode to be released.
Interrupt Enable Flag (IEF)
The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used
to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these
interrupts is accepted, the corresponding bit of the event flag will be reset, but the other bits are
unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I or
EN INT is executed again. Besides, these interrupts can be disable by executing DIS INT instruction.
The bit descriptions are as follows:
76543210
IEF w
w
www
Note: W means write only.
IEF.0 = 1 Interrupt 0 is accepted by overflow from Divider 0.
IEF.1 = 1 Interrupt 1 is accepted by underflow from Timer 0.
IEF.2 = 1 Interrupt 2 is accepted by a signal change on port RC.
IEF.3 Reserved
IEF.4 = 1 Interrupt 4 is accepted by a falling edge signal on the INT pin.
IEF.5 & IEF.6 are reserved.
IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.
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Publication Release Date: March 1998
Revision A2