W25S243A Datasheet, PDF (9/17 Pages) Winbond – 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

Preliminary W25S243A
AC Timing Characteristics, continued
PARAMETER
SYMBOL
ADSP Setup Time
ADSP Hold Time
ADSC Setup Time
ADSC Hold Time
CE1, CE2, CE3 Setup Time
CE1, CE2, CE3 Hold Time
GW , BWE X Setup Time
GW , BWE X Hold Time
Clock Cycle Time
Clock High Pulse Width
Clock Low Pulse Width
Clock to Output Valid
Clock to Output High-Z
Clock to Output Low-Z
Clock to Output Invalid
Output Enable to Output
Valid
Output Enable to Output
High-Z
Output Enable to Output
Low-Z
Output Enable to Output
Invalid
ZZ Standby Time
ZZ Recover Time
TADSS
TADSH
TADCS
TADCH
TCES
TCEH
TWS
TWH
TCYC
TKO
TKL
TKQ
TKHZ
TKLZ
TKX
TOE
TOHZ
TOLZ
TOX
TZZS
TZZR
W25S243A-12
MIN.
MAX.
2.5
-
0.5
-
2.5
-
0.5
-
2.5
-
0.5
-
2.5
-
0.5
-
15
-
6
-
6
-
-
12
2
15
0
-
2
-
-
7
-
7
0
-
0
-
-
100
100
-
UNIT NOTES
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
1
nS
1
nS
1
nS
nS
1
nS
1
nS
nS
2
nS
3
Notes:
1. These parameters are sampled but not 100% tested
2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active.
3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode.
4. Configuration signals LBO and FT are static and should not be changed during operation.
Publication Release Date: November 1998
-9-
Revision A1